[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16

[jkolek]

Summary

Implement disassembler support for microMIPS 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16.

[sstankovic]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1127

lbu16 is wrongly disassembled when encoded immediate is 0xf. The decoded immediate should be -1 in that case. For the following instruction

lbu16 $3, -1($16)

if it is assembled with llvm-mc (or gcc) and then disassembled with llvm-objdump, the result is

lbu16 $3, 15($16)

Please include this instruction in both assemble and disassemble tests.

1134

It's not clear whether you need SignExtend here. Instruction reference document says that offset is sign-extended. But gcc treats the offset as zero-extended, and will only assemble lw16 if offset is [0, 4, ..., 60].

[jkolek]

Corrected LBU16 offset, if offset its encoding is 0xF then disassembled value will be -1.
LW16 is corrected according to GCC.

[sstankovic]

LGTM

[jkolek]

Closed by commit rL222847 (authored by @jkolek).

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 static DecodeStatus DecodeCacheOp(MCInst &Inst,
                               unsigned Insn,
                               uint64_t Address,
                               const void *Decoder);
 
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder);
 
+static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
+                                    unsigned Insn,
+                                    uint64_t Address,
+                                    const void *Decoder);
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder);
 
 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
   Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
                                                    unsigned RegNo,
                                                    uint64_t Address,
                                                    const void *Decoder) {
+  if (RegNo > 7)
     return MCDisassembler::Fail;
+  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
                                              unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
   case Mips::ST_D:
     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
     break;
   }
 
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
+                                    unsigned Insn,
+                                    uint64_t Address,
+                                    const void *Decoder) {
+  unsigned Offset = Insn & 0xf;
+  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
+  unsigned Base = fieldFromInstruction(Insn, 4, 3);
+
+  switch (Inst.getOpcode()) {
+    case Mips::LBU16_MM:
+    case Mips::LHU16_MM:
+    case Mips::LW16_MM:
+      if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
+            == MCDisassembler::Fail)
+        return MCDisassembler::Fail;
+      break;
+    case Mips::SB16_MM:
+    case Mips::SH16_MM:
+    case Mips::SW16_MM:
+      if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
+            == MCDisassembler::Fail)
+        return MCDisassembler::Fail;
+      break;
+  }
+
+  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
+        == MCDisassembler::Fail)
+    return MCDisassembler::Fail;
+
+  switch (Inst.getOpcode()) {
+    case Mips::LBU16_MM:
+      if (Offset == 0xf)
+        Inst.addOperand(MCOperand::CreateImm(-1));
+      else
+        Inst.addOperand(MCOperand::CreateImm(Offset));
+      break;
+    case Mips::SB16_MM:
+      Inst.addOperand(MCOperand::CreateImm(Offset));
+      break;
+    case Mips::LHU16_MM:
+    case Mips::SH16_MM:
+      Inst.addOperand(MCOperand::CreateImm(Offset >> 1));
+      break;
+    case Mips::LW16_MM:
+    case Mips::SW16_MM:
+      Inst.addOperand(MCOperand::CreateImm(Offset >> 2));
+      break;
+  }
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder) {
   int Offset = SignExtend32<12>(Insn & 0x0fff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 

lib/Target/Mips/MicroMipsInstrInfo.td

class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
                  InstrItinClass Itin = NoItinerary> :
   MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
                   !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
 
 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
                InstrItinClass Itin, Operand MemOpnd> :
   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMImm4";
   let canFoldAsLoad = 1;
   let mayLoad = 1;
 }
 
 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
                 SDPatternOperator OpNode, InstrItinClass Itin, Operand MemOpnd> :
   MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMImm4";
   let mayStore = 1;
 }
 
 class AddImmUR2<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
                   !strconcat(opstr, "\t$rd, $rs, $imm"),
                   [], NoItinerary, FrmR> {
   let isCommutable = 1;

lib/Target/Mips/MipsRegisterInfo.td

def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
   // Callee save
   S0, S1,
   // Return Values and Arguments
   V0, V1, A0, A1, A2, A3)>;
 
 def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
   // Reserved
   ZERO,
-  // Return Values and Arguments
-  V0, V1, A0, A1, A2, A3,
   // Callee save
-  S1)>;
+  S1,
+  // Return Values and Arguments
+  V0, V1, A0, A1, A2, A3)>;
 
 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
 // Reserved
   ZERO_64, AT_64,
   // Return Values and Arguments
   V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
   // Not preserved across procedure calls
   T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,

test/MC/Disassembler/Mips/micromips.txt

 0x44 0x4d
 
 # CHECK: sll16 $3, $16, 5
 0x25 0x8a
 
 # CHECK: srl16 $4, $17, 6
 0x26 0x1d
 
+# CHECK: lbu16 $3, 4($17)
+0x09 0x94
+
+# CHECK: lbu16 $3, -1($16)
+0x09 0x8f
+
+# CHECK: lhu16 $3, 4($16)
+0x29 0x82
+
+# CHECK: lw16 $4, 8($17)
+0x6a 0x12
+
+# CHECK: sb16 $3, 4($16)
+0x89 0x84
+
+# CHECK: sh16 $4, 8($17)
+0xaa 0x14
+
+# CHECK: sw16 $4, 4($17)
+0xea 0x11
+
+# CHECK: sw16 $zero, 4($17)
+0xe8 0x11
+
 # CHECK: mfhi $9
 0x46 0x09
 
 # CHECK: mflo $9
 0x46 0x49
 
 # CHECK: move $25, $1
 0x0f 0x21

test/MC/Disassembler/Mips/micromips_le.txt

 0x4d 0x44
 
 # CHECK: sll16 $3, $16, 5
 0x8a 0x25
 
 # CHECK: srl16 $4, $17, 6
 0x1d 0x26
 
+# CHECK: lbu16 $3, 4($17)
+0x94 0x09
+
+# CHECK: lbu16 $3, -1($16)
+0x8f 0x09
+
+# CHECK: lhu16 $3, 4($16)
+0x82 0x29
+
+# CHECK: lw16 $4, 8($17)
+0x12 0x6a
+
+# CHECK: sb16 $3, 4($16)
+0x84 0x89
+
+# CHECK: sh16 $4, 8($17)
+0x14 0xaa
+
+# CHECK: sw16 $4, 4($17)
+0x11 0xea
+
+# CHECK: sw16 $zero, 4($17)
+0x11 0xe8
+
 # CHECK: mfhi $9
 0x09 0x46
 
 # CHECK: mflo $9
 0x49 0x46
 
 # CHECK: move $25, $1
 0x21 0x0f