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Differential D64054

GlobalISel: Add G_FENCE
ClosedPublic

Authored by arsenm on Jul 1 2019, 6:17 PM.

Details

Reviewers
aemerson
aditya_nandakumar
paquette
Summary

The pattern importer is for some reason emitting checks for G_CONSTANT
for the immediate operands.

Diff Detail

Event Timeline

arsenm created this revision.Jul 1 2019, 6:17 PM
Herald added subscribers: Petar.Avramovic, volkan, jfb and 6 others. · View Herald TranscriptJul 1 2019, 6:17 PM
aemerson accepted this revision.Jul 1 2019, 11:50 PM

Can you add an IRTranslator test and commit that separately from the selector changes.

This revision is now accepted and ready to land.Jul 1 2019, 11:50 PM
arsenm closed this revision.Jul 2 2019, 7:17 AM

r364926, 364927

arsenm mentioned this in D61289: [globalisel] Add G_SEXT_INREG.Jul 3 2019, 12:24 PM

Revision Contents

PathSize
include/
llvm/
CodeGen/
GlobalISel/
4 lines
3 lines
Support/
3 lines
Target/
6 lines
GlobalISel/
1 line
lib/
CodeGen/
GlobalISel/
8 lines
7 lines
Target/
AMDGPU/
5 lines
test/
CodeGen/
AArch64/
GlobalISel/
3 lines
AMDGPU/
GlobalISel/
719 lines

Diff 207453

include/llvm/CodeGen/GlobalISel/IRTranslator.h

Show First 20 Lines • Show All 442 Lines • ▼ Show 20 Linesprivate:
bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder); bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder); bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder); bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder); bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder); bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
bool translateFence(const User &U, MachineIRBuilder &MIRBuilder);
// Stubs to keep the compiler happy while we implement the rest of the // Stubs to keep the compiler happy while we implement the rest of the
// translation. // translation.
bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) { bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
} }
bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) { bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
} }
bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) { bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
} }
bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) { bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
} }
bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
return false;
}
bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) { bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder); return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
} }
bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) { bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
} }
bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) { bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
return false; return false;
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Show First 20 Lines • Show All 1,130 Lines • ▼ Show 20 Linespublic:
/// \pre \p Addr must be a generic virtual register with pointer type. /// \pre \p Addr must be a generic virtual register with pointer type.
/// \pre \p OldValRes, and \p Val must be generic virtual registers of the /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
/// same type. /// same type.
/// ///
/// \return a MachineInstrBuilder for the newly created instruction. /// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
Register Val, MachineMemOperand &MMO); Register Val, MachineMemOperand &MMO);
/// Build and insert `G_FENCE Ordering, Scope`.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
/// Build and insert \p Res = G_BLOCK_ADDR \p BA /// Build and insert \p Res = G_BLOCK_ADDR \p BA
/// ///
/// G_BLOCK_ADDR computes the address of a basic block. /// G_BLOCK_ADDR computes the address of a basic block.
/// ///
/// \pre setBasicBlock or setMI must have been called. /// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res must be a generic virtual register of a pointer type. /// \pre \p Res must be a generic virtual register of a pointer type.
/// ///
/// \return The newly created instruction. /// \return The newly created instruction.
▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

include/llvm/Support/TargetOpcodes.def

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Lines
HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
// Generic atomic fence
HANDLE_TARGET_OPCODE(G_FENCE)
/// Generic conditional branch instruction. /// Generic conditional branch instruction.
HANDLE_TARGET_OPCODE(G_BRCOND) HANDLE_TARGET_OPCODE(G_BRCOND)
/// Generic indirect branch instruction. /// Generic indirect branch instruction.
HANDLE_TARGET_OPCODE(G_BRINDIRECT) HANDLE_TARGET_OPCODE(G_BRINDIRECT)
/// Generic intrinsic use (without side effects). /// Generic intrinsic use (without side effects).
HANDLE_TARGET_OPCODE(G_INTRINSIC) HANDLE_TARGET_OPCODE(G_INTRINSIC)
▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines

include/llvm/Target/GenericOpcodes.td

Show First 20 Lines • Show All 737 Lines • ▼ Show 20 Lines
def G_ATOMICRMW_NAND : G_ATOMICRMW_OP; def G_ATOMICRMW_NAND : G_ATOMICRMW_OP;
def G_ATOMICRMW_OR : G_ATOMICRMW_OP; def G_ATOMICRMW_OR : G_ATOMICRMW_OP;
def G_ATOMICRMW_XOR : G_ATOMICRMW_OP; def G_ATOMICRMW_XOR : G_ATOMICRMW_OP;
def G_ATOMICRMW_MAX : G_ATOMICRMW_OP; def G_ATOMICRMW_MAX : G_ATOMICRMW_OP;
def G_ATOMICRMW_MIN : G_ATOMICRMW_OP; def G_ATOMICRMW_MIN : G_ATOMICRMW_OP;
def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP; def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP;
def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP; def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP;
def G_FENCE : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$ordering, i32imm:$scope);
let hasSideEffects = 1;
}
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// Variadic ops // Variadic ops
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// Extract a register of the specified size, starting from the block given by // Extract a register of the specified size, starting from the block given by
// index. This will almost certainly be mapped to sub-register COPYs after // index. This will almost certainly be mapped to sub-register COPYs after
// register banks have been selected. // register banks have been selected.
def G_EXTRACT : GenericInstruction { def G_EXTRACT : GenericInstruction {
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and>; def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and>;
def : GINodeEquiv<G_ATOMICRMW_NAND, atomic_load_nand>; def : GINodeEquiv<G_ATOMICRMW_NAND, atomic_load_nand>;
def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or>; def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or>;
def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor>; def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor>;
def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min>; def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min>;
def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max>; def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max>;
def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin>; def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin>;
def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax>; def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax>;
def : GINodeEquiv<G_FENCE, atomic_fence>;
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern. // Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.
// Should be used on defs that subclass GIComplexOperandMatcher<>. // Should be used on defs that subclass GIComplexOperandMatcher<>.
class GIComplexPatternEquiv<ComplexPattern seldag> { class GIComplexPatternEquiv<ComplexPattern seldag> {
ComplexPattern SelDAGEquivalent = seldag; ComplexPattern SelDAGEquivalent = seldag;
} }
// Specifies the GlobalISel equivalents for SelectionDAG's SDNodeXForm. // Specifies the GlobalISel equivalents for SelectionDAG's SDNodeXForm.
// Should be used on defs that subclass GICustomOperandRenderer<>. // Should be used on defs that subclass GICustomOperandRenderer<>.
class GISDNodeXFormEquiv<SDNodeXForm seldag> { class GISDNodeXFormEquiv<SDNodeXForm seldag> {
SDNodeXForm SelDAGEquivalent = seldag; SDNodeXForm SelDAGEquivalent = seldag;
} }

lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 2,023 Lines • ▼ Show 20 Lines MIRBuilder.buildAtomicRMW(
Opcode, Res, Addr, Val, Opcode, Res, Addr, Val,
*MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
Flags, DL->getTypeStoreSize(ResType), Flags, DL->getTypeStoreSize(ResType),
getMemOpAlignment(I), AAMDNodes(), nullptr, getMemOpAlignment(I), AAMDNodes(), nullptr,
I.getSyncScopeID(), I.getOrdering())); I.getSyncScopeID(), I.getOrdering()));
return true; return true;
} }
bool IRTranslator::translateFence(const User &U,
MachineIRBuilder &MIRBuilder) {
const FenceInst &Fence = cast<FenceInst>(U);
MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
Fence.getSyncScopeID());
return true;
}
void IRTranslator::finishPendingPhis() { void IRTranslator::finishPendingPhis() {
#ifndef NDEBUG #ifndef NDEBUG
DILocationVerifier Verifier; DILocationVerifier Verifier;
GISelObserverWrapper WrapperObserver(&Verifier); GISelObserverWrapper WrapperObserver(&Verifier);
RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver); RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
#endif // ifndef NDEBUG #endif // ifndef NDEBUG
for (auto &Phi : PendingPHIs) { for (auto &Phi : PendingPHIs) {
const PHINode *PI = Phi.first; const PHINode *PI = Phi.first;
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Show First 20 Lines • Show All 845 Lines • ▼ Show 20 Lines
MachineInstrBuilder MachineInstrBuilder
MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr, MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
Register Val, MachineMemOperand &MMO) { Register Val, MachineMemOperand &MMO) {
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val, return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
MMO); MMO);
} }
MachineInstrBuilder MachineInstrBuilder
MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
buildInstr(TargetOpcode::G_FENCE)
.addImm(Ordering)
.addImm(Scope);
}
MachineInstrBuilder
MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) { MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
#ifndef NDEBUG #ifndef NDEBUG
assert(getMRI()->getType(Res).isPointer() && "invalid res type"); assert(getMRI()->getType(Res).isPointer() && "invalid res type");
#endif #endif
return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
} }
▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 1,174 Lines • ▼ Show 20 Lines if (selectG_SZA_EXT(I)) {
return true; return true;
} }
return false; return false;
case TargetOpcode::G_BRCOND: case TargetOpcode::G_BRCOND:
return selectG_BRCOND(I); return selectG_BRCOND(I);
case TargetOpcode::G_FRAME_INDEX: case TargetOpcode::G_FRAME_INDEX:
return selectG_FRAME_INDEX(I); return selectG_FRAME_INDEX(I);
case TargetOpcode::G_FENCE:
// FIXME: Tablegen importer doesn't handle the imm operands correctly, and
// is checking for G_CONSTANT
I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));
return true;
} }
return false; return false;
} }
InstructionSelector::ComplexRendererFns InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const { AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
return {{ return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); } [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
▲ Show 20 Lines • Show All 152 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
# #
# DEBUG-NEXT: G_ATOMICRMW_UMAX (opcode {{[0-9]+}}): 2 type indices # DEBUG-NEXT: G_ATOMICRMW_UMAX (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
# #
# DEBUG-NEXT: G_ATOMICRMW_UMIN (opcode {{[0-9]+}}): 2 type indices # DEBUG-NEXT: G_ATOMICRMW_UMIN (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
# #
# DEBUG-NEXT: G_FENCE (opcode {{[0-9]+}}): 0 type indices
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_BRCOND (opcode {{[0-9]+}}): 1 type index # DEBUG-NEXT: G_BRCOND (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. the first uncovered type index: 1, OK # DEBUG: .. the first uncovered type index: 1, OK
# #
# DEBUG-NEXT: G_BRINDIRECT (opcode {{[0-9]+}}): 1 type index # DEBUG-NEXT: G_BRINDIRECT (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. the first uncovered type index: 1, OK # DEBUG: .. the first uncovered type index: 1, OK
# #
# DEBUG-NEXT: G_INTRINSIC (opcode {{[0-9]+}}): 0 type indices # DEBUG-NEXT: G_INTRINSIC (opcode {{[0-9]+}}): 0 type indices
# DEBUG: .. type index coverage check SKIPPED: no rules defined # DEBUG: .. type index coverage check SKIPPED: no rules defined
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll

  • This file was added.
; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
; FUNC-LABEL: {{^}}system_one_as_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
; GFX10: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_one_as_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_acquire() {
entry:
fence syncscope("one-as") acquire
ret void
}
; FUNC-LABEL: {{^}}system_one_as_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_one_as_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_release() {
entry:
fence syncscope("one-as") release
ret void
}
; FUNC-LABEL: {{^}}system_one_as_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_one_as_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_acq_rel() {
entry:
fence syncscope("one-as") acq_rel
ret void
}
; FUNC-LABEL: {{^}}system_one_as_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_one_as_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_seq_cst() {
entry:
fence syncscope("one-as") seq_cst
ret void
}
; FUNC-LABEL: {{^}}singlethread_one_as_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_one_as_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acquire() {
entry:
fence syncscope("singlethread-one-as") acquire
ret void
}
; FUNC-LABEL: {{^}}singlethread_one_as_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_one_as_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_release() {
entry:
fence syncscope("singlethread-one-as") release
ret void
}
; FUNC-LABEL: {{^}}singlethread_one_as_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_one_as_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acq_rel() {
entry:
fence syncscope("singlethread-one-as") acq_rel
ret void
}
; FUNC-LABEL: {{^}}singlethread_one_as_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_one_as_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_seq_cst() {
entry:
fence syncscope("singlethread-one-as") seq_cst
ret void
}
; FUNC-LABEL: {{^}}agent_one_as_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
; GFX10: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_one_as_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acquire() {
entry:
fence syncscope("agent-one-as") acquire
ret void
}
; FUNC-LABEL: {{^}}agent_one_as_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_one_as_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_release() {
entry:
fence syncscope("agent-one-as") release
ret void
}
; FUNC-LABEL: {{^}}agent_one_as_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_one_as_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acq_rel() {
entry:
fence syncscope("agent-one-as") acq_rel
ret void
}
; FUNC-LABEL: {{^}}agent_one_as_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_one_as_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_seq_cst() {
entry:
fence syncscope("agent-one-as") seq_cst
ret void
}
; FUNC-LABEL: {{^}}workgroup_one_as_acquire:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_one_as_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_one_as_acquire() {
entry:
fence syncscope("workgroup-one-as") acquire
ret void
}
; FUNC-LABEL: {{^}}workgroup_one_as_release:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NOT: buffer_gl0_inv
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_one_as_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_one_as_release() {
entry:
fence syncscope("workgroup-one-as") release
ret void
}
; FUNC-LABEL: {{^}}workgroup_one_as_acq_rel:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_one_as_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_one_as_acq_rel() {
entry:
fence syncscope("workgroup-one-as") acq_rel
ret void
}
; FUNC-LABEL: {{^}}workgroup_one_as_seq_cst:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_one_as_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_one_as_seq_cst() {
entry:
fence syncscope("workgroup-one-as") seq_cst
ret void
}
; FUNC-LABEL: {{^}}wavefront_one_as_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_one_as_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_one_as_acquire() {
entry:
fence syncscope("wavefront-one-as") acquire
ret void
}
; FUNC-LABEL: {{^}}wavefront_one_as_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_one_as_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_one_as_release() {
entry:
fence syncscope("wavefront-one-as") release
ret void
}
; FUNC-LABEL: {{^}}wavefront_one_as_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_one_as_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_one_as_acq_rel() {
entry:
fence syncscope("wavefront-one-as") acq_rel
ret void
}
; FUNC-LABEL: {{^}}wavefront_one_as_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_one_as_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_one_as_seq_cst() {
entry:
fence syncscope("wavefront-one-as") seq_cst
ret void
}
; FUNC-LABEL: {{^}}system_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_acquire() {
entry:
fence acquire
ret void
}
; FUNC-LABEL: {{^}}system_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_release() {
entry:
fence release
ret void
}
; FUNC-LABEL: {{^}}system_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_acq_rel() {
entry:
fence acq_rel
ret void
}
; FUNC-LABEL: {{^}}system_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel system_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_seq_cst() {
entry:
fence seq_cst
ret void
}
; FUNC-LABEL: {{^}}singlethread_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_acquire() {
entry:
fence syncscope("singlethread") acquire
ret void
}
; FUNC-LABEL: {{^}}singlethread_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_release() {
entry:
fence syncscope("singlethread") release
ret void
}
; FUNC-LABEL: {{^}}singlethread_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_acq_rel() {
entry:
fence syncscope("singlethread") acq_rel
ret void
}
; FUNC-LABEL: {{^}}singlethread_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel singlethread_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_seq_cst() {
entry:
fence syncscope("singlethread") seq_cst
ret void
}
; FUNC-LABEL: {{^}}agent_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_acquire() {
entry:
fence syncscope("agent") acquire
ret void
}
; FUNC-LABEL: {{^}}agent_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_release() {
entry:
fence syncscope("agent") release
ret void
}
; FUNC-LABEL: {{^}}agent_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_acq_rel() {
entry:
fence syncscope("agent") acq_rel
ret void
}
; FUNC-LABEL: {{^}}agent_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX8: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX6: buffer_wbinvl1{{$}}
; GFX8: buffer_wbinvl1_vol{{$}}
; GFX10-NEXT: buffer_gl0_inv{{$}}
; GFX10-NEXT: buffer_gl1_inv{{$}}
; GCN: s_endpgm
; GFX10: .amdhsa_kernel agent_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_seq_cst() {
entry:
fence syncscope("agent") seq_cst
ret void
}
; FUNC-LABEL: {{^}}workgroup_acquire:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_acquire() {
entry:
fence syncscope("workgroup") acquire
ret void
}
; FUNC-LABEL: {{^}}workgroup_release:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10-NOT: buffer_gl0_inv
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_release() {
entry:
fence syncscope("workgroup") release
ret void
}
; FUNC-LABEL: {{^}}workgroup_acq_rel:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_acq_rel() {
entry:
fence syncscope("workgroup") acq_rel
ret void
}
; FUNC-LABEL: {{^}}workgroup_seq_cst:
; GCN: %bb.0
; GFX68-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10WGP: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10WGP-NEXT: buffer_gl0_inv{{$}}
; GFX10CU-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10CU-NOT: s_waitcnt_vscnt null, 0x0{{$}}
; GFX10CU-NOT: buffer_gl0_inv{{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel workgroup_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @workgroup_seq_cst() {
entry:
fence syncscope("workgroup") seq_cst
ret void
}
; FUNC-LABEL: {{^}}wavefront_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_acquire
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_acquire() {
entry:
fence syncscope("wavefront") acquire
ret void
}
; FUNC-LABEL: {{^}}wavefront_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_release
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_release() {
entry:
fence syncscope("wavefront") release
ret void
}
; FUNC-LABEL: {{^}}wavefront_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_acq_rel
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_acq_rel() {
entry:
fence syncscope("wavefront") acq_rel
ret void
}
; FUNC-LABEL: {{^}}wavefront_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
; GFX10: .amdhsa_kernel wavefront_seq_cst
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @wavefront_seq_cst() {
entry:
fence syncscope("wavefront") seq_cst
ret void
}