This is an archive of the discontinued LLVM Phabricator instance.

Differential D64004

AArch64/GlobalISel: Fix trying to select invalid MIR
ClosedPublic

Authored by arsenm on Jul 1 2019, 5:51 AM.

Details

Reviewers
aemerson
paquette
aditya_nandakumar
Summary

Physical registers are not allowed to be a phi operand.

Diff Detail

Event Timeline

arsenm created this revision.Jul 1 2019, 5:51 AM
Herald added subscribers: Petar.Avramovic, kristof.beyls, javed.absar and 2 others. · View Herald TranscriptJul 1 2019, 5:51 AM
paquette accepted this revision.Jul 1 2019, 9:43 AM

LGTM

This revision is now accepted and ready to land.Jul 1 2019, 9:43 AM
arsenm closed this revision.Jul 1 2019, 10:02 AM

r364810

Revision Contents

PathSize
lib/
Target/
AArch64/
33 lines

Diff 207281

lib/Target/AArch64/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 1,058 Lines • ▼ Show 20 Lines if (!isPreISelGenericOpcode(Opcode) || Opcode == TargetOpcode::G_PHI) {
if (Opcode == TargetOpcode::LOAD_STACK_GUARD) if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
return constrainSelectedInstRegOperands(I, TII, TRI, RBI); return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) { if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) {
const Register DefReg = I.getOperand(0).getReg(); const Register DefReg = I.getOperand(0).getReg();
const LLT DefTy = MRI.getType(DefReg); const LLT DefTy = MRI.getType(DefReg);
const TargetRegisterClass *DefRC = nullptr;
if (TargetRegisterInfo::isPhysicalRegister(DefReg)) {
DefRC = TRI.getRegClass(DefReg);
} else {
const RegClassOrRegBank &RegClassOrBank = const RegClassOrRegBank &RegClassOrBank =
MRI.getRegClassOrRegBank(DefReg); MRI.getRegClassOrRegBank(DefReg);
DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); const TargetRegisterClass *DefRC
= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
if (!DefRC) { if (!DefRC) {
if (!DefTy.isValid()) { if (!DefTy.isValid()) {
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
return false; return false;
} }
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
if (!DefRC) { if (!DefRC) {
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
return false; return false;
} }
} }
}
I.setDesc(TII.get(TargetOpcode::PHI)); I.setDesc(TII.get(TargetOpcode::PHI));
return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
} }
if (I.isCopy()) if (I.isCopy())
return selectCopy(I, TII, MRI, TRI, RBI); return selectCopy(I, TII, MRI, TRI, RBI);
▲ Show 20 Lines • Show All 2,689 Lines • Show Last 20 Lines