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Differential D63903

[InstCombine][NFCI] Update test cases in onehot_merge.ll
ClosedPublic

Authored by huihuiz on Jun 27 2019, 4:09 PM.

Details

Reviewers
lebedev.ri
spatel
efriedma
craig.topper
Commits
rG8e1051b3a02d: [InstCombine][NFCI] Update test cases in onehot_merge.ll
rL364857: [InstCombine][NFCI] Update test cases in onehot_merge.ll
Summary

Use both one bit and signbit shifting to check for one bit merge.

Diff Detail

Repository
rL LLVM

Event Timeline

huihuiz created this revision.Jun 27 2019, 4:09 PM
huihuiz added a parent revision: D62818: [InstCombine] Introduce fold for icmp pred (and X, (sh signbit, Y)), 0..
huihuiz mentioned this in D62818: [InstCombine] Introduce fold for icmp pred (and X, (sh signbit, Y)), 0..Jun 27 2019, 4:18 PM
lebedev.ri accepted this revision.Jul 1 2019, 2:21 PM

It is okay to add new tests without review, please land this.
I've now encountered this too :S

This revision is now accepted and ready to land.Jul 1 2019, 2:21 PM
Closed by commit rL364857: [InstCombine][NFCI] Update test cases in onehot_merge.ll (authored by huihuiz). · Explain WhyJul 1 2019, 3:04 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
Transforms/
InstCombine/
54 lines

Diff 207416

llvm/trunk/test/Transforms/InstCombine/onehot_merge.ll

Show All 12 Lines;
%t6 = icmp eq i32 %t5, 0 %t6 = icmp eq i32 %t5, 0
%or = or i1 %t2, %t6 %or = or i1 %t2, %t6
ret i1 %or ret i1 %or
} }
define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_and( ; CHECK-LABEL: @foo1_and(
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]] ; CHECK-NEXT: ret i1 [[TMP3]]
; ;
%t = shl i32 1, %c1 %t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2 %t4 = shl i32 1, %c2
%t1 = and i32 %t, %k %t1 = and i32 %t, %k
%t2 = icmp eq i32 %t1, 0 %t2 = icmp eq i32 %t1, 0
%t5 = and i32 %t4, %k %t5 = and i32 %t4, %k
%t6 = icmp eq i32 %t5, 0 %t6 = icmp eq i32 %t5, 0
%or = or i1 %t2, %t6 %or = or i1 %t2, %t6
ret i1 %or ret i1 %or
} }
; Same as above but with operands commuted one of the ands, but not the other. ; Same as above but with operands commuted one of the ands, but not the other.
define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_and_commuted( ; CHECK-LABEL: @foo1_and_commuted(
; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]] ; CHECK-NEXT: ret i1 [[TMP3]]
; ;
%k2 = mul i32 %k, %k ; to trick the complexity sorting %k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1 %t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2 %t4 = shl i32 1, %c2
%t1 = and i32 %k2, %t %t1 = and i32 %k2, %t
%t2 = icmp eq i32 %t1, 0 %t2 = icmp eq i32 %t1, 0
%t5 = and i32 %t4, %k2 %t5 = and i32 %t4, %k2
%t6 = icmp eq i32 %t5, 0 %t6 = icmp eq i32 %t5, 0
%or = or i1 %t2, %t6 %or = or i1 %t2, %t6
ret i1 %or ret i1 %or
} }
Show All 9 Lines;
%t6 = icmp ne i32 %t5, 0 %t6 = icmp ne i32 %t5, 0
%or = and i1 %t2, %t6 %or = and i1 %t2, %t6
ret i1 %or ret i1 %or
} }
define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_or( ; CHECK-LABEL: @foo1_or(
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]] ; CHECK-NEXT: ret i1 [[TMP3]]
; ;
%t = shl i32 1, %c1 %t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2 %t4 = shl i32 1, %c2
%t1 = and i32 %t, %k %t1 = and i32 %t, %k
%t2 = icmp ne i32 %t1, 0 %t2 = icmp ne i32 %t1, 0
%t5 = and i32 %t4, %k %t5 = and i32 %t4, %k
%t6 = icmp ne i32 %t5, 0 %t6 = icmp ne i32 %t5, 0
%or = and i1 %t2, %t6 %or = and i1 %t2, %t6
ret i1 %or ret i1 %or
} }
; Same as above but with operands commuted one of the ors, but not the other. ; Same as above but with operands commuted one of the ors, but not the other.
define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_or_commuted( ; CHECK-LABEL: @foo1_or_commuted(
; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]] ; CHECK-NEXT: ret i1 [[TMP3]]
; ;
%k2 = mul i32 %k, %k ; to trick the complexity sorting %k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1 %t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2 %t4 = shl i32 1, %c2
%t1 = and i32 %k2, %t %t1 = and i32 %k2, %t
%t2 = icmp ne i32 %t1, 0 %t2 = icmp ne i32 %t1, 0
%t5 = and i32 %t4, %k2 %t5 = and i32 %t4, %k2
%t6 = icmp ne i32 %t5, 0 %t6 = icmp ne i32 %t5, 0
%or = and i1 %t2, %t6 %or = and i1 %t2, %t6
ret i1 %or ret i1 %or
} }
define i1 @foo1_and_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_and_signbit_lshr(
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
%t1 = and i32 %t, %k
%t2 = icmp eq i32 %t1, 0
%t5 = and i32 %t4, %k
%t6 = icmp eq i32 %t5, 0
%or = or i1 %t2, %t6
ret i1 %or
}
define i1 @foo1_or_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_or_signbit_lshr(
; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
%t1 = and i32 %t, %k
%t2 = icmp ne i32 %t1, 0
%t5 = and i32 %t4, %k
%t6 = icmp ne i32 %t5, 0
%or = and i1 %t2, %t6
ret i1 %or
}