AMDGPU/GlobalISel: Use and instead of BFE with inline immediate

[arsenm]

Summary

Zext from s1 is the only case where this should do anything with the
current legal extensions.

[nhaehnle]

Thanks, LGTM

[arsenm]

r364760

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
     LLVM_DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
     return false;
   }
 
   I.setDesc(TII.get(TargetOpcode::COPY));
   return true;
 }
 
+/// \returns true if a bitmask for \p Size bits will be an inline immediate.
+static bool shouldUseAndMask(unsigned Size, unsigned &Mask) {
+  Mask = maskTrailingOnes<unsigned>(Size);
+  int SignedMask = static_cast<int>(Mask);
+  return SignedMask >= -16 && SignedMask <= 64;
+}
+
 bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
   bool Signed = I.getOpcode() == AMDGPU::G_SEXT;
   const DebugLoc &DL = I.getDebugLoc();
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const unsigned DstReg = I.getOperand(0).getReg();
   const unsigned SrcReg = I.getOperand(1).getReg();
if (SrcBank->getID() == AMDGPU::VCCRegBankID && DstSize <= 32) {
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
 
   if (I.getOpcode() == AMDGPU::G_ANYEXT)
     return selectCOPY(I);
 
   if (SrcBank->getID() == AMDGPU::VGPRRegBankID && DstSize <= 32) {
     // 64-bit should have been split up in RegBankSelect
-    //
-    // TODO: USE V_AND_B32 when the constant mask is an inline immediate for
-    // unsigned for smaller code size.
+
+    // Try to use an and with a mask if it will save code size.
+    unsigned Mask;
+    if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
+      MachineInstr *ExtI =
+      BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
+        .addImm(Mask)
+        .addReg(SrcReg);
+      return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
+    }
+
     const unsigned BFE = Signed ? AMDGPU::V_BFE_I32 : AMDGPU::V_BFE_U32;
     MachineInstr *ExtI =
       BuildMI(MBB, I, DL, TII.get(BFE), DstReg)
       .addReg(SrcReg)
       .addImm(0) // Offset
       .addImm(SrcSize); // Width
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
if (DstSize > 32 && SrcSize <= 32) {
 
       BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
         .addReg(ExtReg)
         .addImm(SrcSize << 16);
 
       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
     }
 
+    unsigned Mask;
+    if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
+      BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
+        .addReg(SrcReg)
+        .addImm(Mask);
+    } else {
       BuildMI(MBB, I, DL, TII.get(BFE32), DstReg)
         .addReg(SrcReg)
         .addImm(SrcSize << 16);
+    }
+
     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
   }
 
   return false;
 }
 
 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();

test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

bb.0:
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s64) = G_ANYEXT %1
     $sgpr0_sgpr1 = COPY %2
 ...
 
 ---
 
+name: anyext_sgpr_s8_to_sgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32
+    ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s8) = G_TRUNC %0
+    %2:sgpr(s32) = G_ANYEXT %1
+    $sgpr0 = COPY %2
+
+...
+
+---
+
 name: anyext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
bb.0:
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s1) = G_TRUNC %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 
+name: anyext_vgpr_s8_to_vgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: anyext_vgpr_s8_to_vgpr_s32
+    ; GCN: $vgpr0 = COPY %2:vgpr_32
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s8) = G_TRUNC %0
+    %2:vgpr(s32) = G_ANYEXT %1
+    $vgpr0 = COPY %2
+
+...
+
+---
+
 name: anyext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
     ; GCN: $vgpr0 = COPY %2:vgpr_32
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 
 ...

test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

bb.0:
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s64) = G_SEXT %1
     $sgpr0_sgpr1 = COPY %2
 ...
 
 ---
 
+name: sext_sgpr_s8_to_sgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: sext_sgpr_s8_to_sgpr_s32
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[S_SEXT_I32_I8_:%[0-9]+]]:sreg_32_xm0 = S_SEXT_I32_I8 [[COPY]]
+    ; GCN: $sgpr0 = COPY [[S_SEXT_I32_I8_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s8) = G_TRUNC %0
+    %2:sgpr(s32) = G_SEXT %1
+    $sgpr0 = COPY %2
+...
+
+---
+
 name: sext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s32
bb.0:
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s1) = G_TRUNC %0
     %2:vgpr(s32) = G_SEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 
+name: sext_vgpr_s8_to_vgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: sext_vgpr_s8_to_vgpr_s32
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[V_BFE_I32_:%[0-9]+]]:vgpr_32 = V_BFE_I32 [[COPY]], 0, 8, implicit $exec
+    ; GCN: $vgpr0 = COPY [[V_BFE_I32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s8) = G_TRUNC %0
+    %2:vgpr(s32) = G_SEXT %1
+    $vgpr0 = COPY %2
+
+...
+
+---
+
 name: sext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: sext_vgpr_s16_to_vgpr_s32

test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
     ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32_xm0 = S_BFE_U32 [[COPY]], 65536, implicit-def $scc
-    ; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
+    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], 1, implicit-def $scc
+    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s32) = G_ZEXT %1
     $sgpr0 = COPY %2
 ...
 
 ---
 
bb.0:
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s64) = G_ZEXT %1
     $sgpr0_sgpr1 = COPY %2
 ...
 
 ---
 
+name: zext_sgpr_s8_to_sgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: zext_sgpr_s8_to_sgpr_s32
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32_xm0 = S_BFE_U32 [[COPY]], 524288, implicit-def $scc
+    ; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s8) = G_TRUNC %0
+    %2:sgpr(s32) = G_ZEXT %1
+    $sgpr0 = COPY %2
+
+...
+
+---
+
 name: zext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32

 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[COPY]], 0, 1, implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_BFE_U32_]]
+    ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
+    ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s1) = G_TRUNC %0
     %2:vgpr(s32) = G_ZEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 
+name: zext_vgpr_s8_to_vgpr_s32
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: zext_vgpr_s8_to_vgpr_s32
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[COPY]], 0, 8, implicit $exec
+    ; GCN: $vgpr0 = COPY [[V_BFE_U32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s8) = G_TRUNC %0
+    %2:vgpr(s32) = G_ZEXT %1
+    $vgpr0 = COPY %2
+
+...
+
+---
+
 name: zext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32