[InstCombine] cttz(-x) -> cttz(x)

[xbolva00]

Summary

Signedness does not change number of trailing zeros.

[xbolva00]

Rebased.

[xbolva00]

Rebased, added tests.

[xbolva00]

Uploaded correct patch.

[spatel]

Is 'nsw' a requirement? If not, the tests should not include that, or at least not *all* of the tests should include that.

The latest version of Alive can verify this, but not the online version?

[xbolva00]

I built z3 and Alive2 trunks for Ubuntu 18.04

I took example
Name: cttz constant
%r = cttz i8 32, i1 0

=>

%r = 5

~/alive2/build$ ./alive -root-only c.opt
Processing c.opt..

It never stops..

Edit: I tried 4.8.1 too. Alive2's master branch broken?

[xbolva00]

Drop nsw

[spatel]

LGTM

test/Transforms/InstCombine/cttz-negative.ll

19–20

It would be better if at least 1 of these tests showed an extra use of the negated value. That would verify that we still do the transform independently of uses of that value.

[xbolva00]

Added "multi use" test.

lib/Transforms/InstCombine/InstCombineCalls.cpp

static Instruction *foldCttzCtlz(IntrinsicInst &II, InstCombiner &IC) {
   // ctlz(bitreverse(x)) -> cttz(x)
   // cttz(bitreverse(x)) -> ctlz(x)
   if (match(Op0, m_BitReverse(m_Value(X)))) {
     Intrinsic::ID ID = IsTZ ? Intrinsic::ctlz : Intrinsic::cttz;
     Function *F = Intrinsic::getDeclaration(II.getModule(), ID, II.getType());
     return CallInst::Create(F, {X, II.getArgOperand(1)});
   }
 
+  // cttz(-x) -> cttz(x)
+  if (IsTZ && match(Op0, m_Neg(m_Value(X)))) {
+    II.setOperand(0, X);
+    return ⅈ
+  }
+
   KnownBits Known = IC.computeKnownBits(Op0, 0, &II);
 
   // Create a mask for bits above (ctlz) or below (cttz) the first known one.
   unsigned PossibleZeros = IsTZ ? Known.countMaxTrailingZeros()
                                 : Known.countMaxLeadingZeros();
   unsigned DefiniteZeros = IsTZ ? Known.countMinTrailingZeros()
                                 : Known.countMinLeadingZeros();
 

test/Transforms/InstCombine/cttz-negative.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define i32 @cttz_neg_value(i32 %x) {
+; CHECK-LABEL: @cttz_neg_value(
+; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT:    ret i32 [[B]]
+;
+  %a = sub nsw i32 0, %x
+  %b = tail call i32 @llvm.cttz.i32(i32 %a)
+  ret i32 %b
+}
+
+define i64 @cttz_neg_value_64(i64 %x) {
+; CHECK-LABEL: @cttz_neg_value_64(
+; CHECK-NEXT:    [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 true), !range !1
+; CHECK-NEXT:    ret i64 [[B]]
+;
+  %a = sub nsw i64 0, %x
+  %b = tail call i64 @llvm.cttz.i64(i64 %a, i1 true)
+  ret i64 %b
+}
+
+define i64 @cttz_neg_value2_64(i64 %x) {
+; CHECK-LABEL: @cttz_neg_value2_64(
+; CHECK-NEXT:    [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT:    ret i64 [[B]]
+;
+  %a = sub nsw i64 0, %x
+  %b = tail call i64 @llvm.cttz.i64(i64 %a, i1 false)
+  ret i64 %b
+}
+
+define <2 x i64> @cttz_neg_value_vec(<2 x i64> %x) {
+; CHECK-LABEL: @cttz_neg_value_vec(
+; CHECK-NEXT:    [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = sub nsw  <2 x i64> zeroinitializer, %x
+  %b = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a)
+  ret <2 x i64> %b
+}
+
+; Negative tests
+
+define i32 @cttz_nonneg_value(i32 %x) {
+; CHECK-LABEL: @cttz_nonneg_value(
+; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 1, [[X:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 false), !range !0
+; CHECK-NEXT:    ret i32 [[B]]
+;
+  %a = sub nsw i32 1, %x
+  %b = tail call i32 @llvm.cttz.i32(i32 %a)
+  ret i32 %b
+}
+
+define <2 x i64> @cttz_nonneg_value_vec(<2 x i64> %x) {
+; CHECK-LABEL: @cttz_nonneg_value_vec(
+; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i64> <i64 1, i64 0>, [[X:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[A]], i1 false)
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = sub nsw  <2 x i64> <i64 1, i64 0>, %x
+  %b = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a)
+  ret <2 x i64> %b
+}
+
+declare i32 @llvm.cttz.i32(i32)
+declare i64 @llvm.cttz.i64(i64, i1)
+declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)