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[MachinePipeliner] Don't check boundary node in checkValidNodeOrder
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Authored by jsji on Jun 13 2019, 10:05 AM.

Details

Summary

This was exposed by PowerPC target enablement - caught by Asan build.

In ScheduleDAG, if we haven't seen any uses in this scheduling region,
we will create a dependence edge to ExitSU to model the live-out latency.
This is required for vreg defs with no in-region use, and prefetches with
no vreg def.

eg:

SU(6):   %4:g8rc = COPY %17:g8rc_and_g8rc_nox0
  # preds left       : 2
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 2
  Depth              : 10
  Height             : 1
  Predecessors:
    SU(5): Data Latency=1 Reg=%17
    SU(2): Anti Latency=1
  Successors:
    ExitSU: Ord  Latency=1 Artificial

When we build NodeOrder in Scheduler, we ignore these boundary nodes.
However, when we check Succs in checkValidNodeOrder, we did not skip
them, but we still assume all the nodes have been sorted and in order in
Indices array, so we lower_bound() will return Indices.end(), causing
memory issues.

Diff Detail

Repository
rL LLVM

Event Timeline

jsji created this revision.Jun 13 2019, 10:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 13 2019, 10:05 AM
hfinkel accepted this revision.Jun 13 2019, 1:14 PM

LGTM

llvm/lib/CodeGen/MachinePipeliner.cpp
3736 ↗(On Diff #204555)

space after , before std.

This revision is now accepted and ready to land.Jun 13 2019, 1:14 PM
jsji marked an inline comment as done.Jun 13 2019, 2:06 PM

Thanks. Will update the comments in commit.

This revision was automatically updated to reflect the committed changes.