This was exposed by PowerPC target enablement - caught by Asan build.
In ScheduleDAG, if we haven't seen any uses in this scheduling region,
we will create a dependence edge to ExitSU to model the live-out latency.
This is required for vreg defs with no in-region use, and prefetches with
no vreg def.
SU(6): %4:g8rc = COPY %17:g8rc_and_g8rc_nox0 # preds left : 2 # succs left : 1 # rdefs left : 0 Latency : 2 Depth : 10 Height : 1 Predecessors: SU(5): Data Latency=1 Reg=%17 SU(2): Anti Latency=1 Successors: ExitSU: Ord Latency=1 Artificial
When we build NodeOrder in Scheduler, we ignore these boundary nodes.
However, when we check Succs in checkValidNodeOrder, we did not skip
them, but we still assume all the nodes have been sorted and in order in
Indices array, so we lower_bound() will return Indices.end(), causing