[PowerPC][HTM] Fix $zero is not a GPRC register for builtin_ttest

[jsji]

Summary

This was found during HTM cleanup.
Adding a test for builtin_ttest would expose following issue.

• • Bad machine code: Illegal physical register for instruction ***
• function: test10
• basic block: %bb.0 entry (0xf0e57497b58)
• instruction: %5:crrc0 = TABORTWCI 0, $zero, 0
• operand 2: $zero

$zero is not a GPRC register.
LLVM ERROR: Found 1 machine code errors.

[hfinkel]

Indeed. Doesn't look like R0 is special there. LGTM.

llvm/lib/Target/PowerPC/PPCInstrHTM.td

 
 def : Pat<(int_ppc_tresume),
           (TSR 1)>;
 
 def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
+          (RLDICL (i64 (COPY (TABORTWCI 0, (LI 0), 0))), 36, 28)>;
 
 } // [HasHTM]

llvm/test/CodeGen/PowerPC/htm.ll

 declare i64 @llvm.ppc.get.tfiar()
 
 define void @test10() {
 entry:
   %0 = tail call i32 @llvm.ppc.tcheck()
   %1 = tail call i32 @llvm.ppc.treclaim(i32 5)
   %2 = tail call i32 @llvm.ppc.trechkpt()
   %3 = tail call i32 @llvm.ppc.tsr(i32 1)
+  %4 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test10
 ; CHECK: tcheck [[REG1:[0-9]+]] 
 ; CHECK: treclaim. [[REG2:[0-9]+]] 
 ; CHECK: trechkpt. 
 ; CHECK: tsr.  1
+; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
 declare i32 @llvm.ppc.tcheck()
 declare i32 @llvm.ppc.treclaim(i32)
 declare i32 @llvm.ppc.trechkpt()
 declare i32 @llvm.ppc.tsr(i32)
+declare i64 @llvm.ppc.ttest()