[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).

[huihuiz]

Summary

For icmp pred (and (sh X, Y), C), 0

  When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
  rather than (X & (signbit >> Y)) != 0.

  When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
  rather than (X & (~C >> Y)) == 0.

For icmp pred (and X, (sh signbit, Y)), 0

  Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
  Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0

[huihuiz]

D62818
Split D62818 into 4 differentials.

[lebedev.ri]

Please land this, it can be adjusted later if needed.

[huihuiz]

Merged

[lebedev.ri]

Hmm, which commit? Could you just use either arc patch, or manually add Differential Revision: <link> so that there is a reference between them?

[huihuiz]

In D63025#1544768, @lebedev.ri wrote:

Hmm, which commit? Could you just use either arc patch, or manually add Differential Revision: <link> so that there is a reference between them?

Hey @lebedev.ri , my apology for this confusion.
The Differential Revision: <link> was added in the commit message.

I did try using "arc patch D*" , but all the tests were added into a new directory , not under the "llvm/test/". So I used "git llvm push" instead.
the commit number is "llvm-svn: 363479"

Sorry about any confusion I might have caused.
Thank you so much again for all your review feedback, really appreciate it!

test/Transforms/InstCombine/icmp-shift-and-negC.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+
+; FIXME: expect ((X << Y) & ~C) ==/!= 0 -> (X << Y) </>= C+1; C+1 is power of 2
+define i1 @shl-and-negC(i32 %x, i32 %y) {
+; CHECK-LABEL: @shl-and-negC(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 -8, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, 4294967288  ; ~7
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+; FIXME: expect ((X l>> Y) & ~C) ==/!= 0 -> (X l>> Y) </>= C+1; C+1 is power of 2
+define i1 @lshr-and-negC(i32 %x, i32 %y) {
+; CHECK-LABEL: @lshr-and-negC(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 -8, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %lshr = lshr i32 %x, %y
+  %and = and i32 %lshr, 4294967288  ; ~7
+  %r = icmp eq i32 %and, 0
+  ret i1 %r
+}

test/Transforms/InstCombine/icmp-shift-and-signbit.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; FIXME: expect ((X << Y) & signbit) ==/!= 0 -> (X << Y) >=/< 0
+define i1 @shl-and-signbit(i32 %x, i32 %y) {
+; CHECK-LABEL: @shl-and-signbit(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, -2147483648
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+; FIXME: expect ((X l>> Y) & signbit) ==/!= 0 -> (X l>> Y) >=/< 0
+define i1 @lshr-and-signbit(i32 %x, i32 %y) {
+; CHECK-LABEL: @lshr-and-signbit(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %lshr = lshr i32 %x, %y
+  %and = and i32 %lshr, -2147483648
+  %r = icmp eq i32 %and, 0
+  ret i1 %r
+}