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Differential D62902

[MIPS GlobalISel] Select fpext and fptrunc
ClosedPublic

Authored by Petar.Avramovic on Jun 5 2019, 7:36 AM.

Details

Reviewers
atanasyan
petarj
Commits
rGa7d000644745: [MIPS GlobalISel] Select fpext and fptrunc
rL362689: [MIPS GlobalISel] Select fpext and fptrunc
Summary

Select G_FPEXT and G_FPTRUNC for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Jun 5 2019, 7:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2019, 7:36 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 3 others. · View Herald Transcript
atanasyan accepted this revision.Jun 5 2019, 1:10 PM

LGTM

This revision is now accepted and ready to land.Jun 5 2019, 1:10 PM
Closed by commit rL362689: [MIPS GlobalISel] Select fpext and fptrunc (authored by Petar.Avramovic). · Explain WhyJun 6 2019, 2:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
6 lines
8 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
65 lines
legalizer/
61 lines
llvm-ir/
25 lines
regbankselect/
63 lines

Diff 203309

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_FCMP) getActionDefinitionsBuilder(G_FCMP)
.legalFor({{s32, s32}, {s32, s64}}) .legalFor({{s32, s32}, {s32, s64}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}) getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
.libcallFor({s32, s64}); .libcallFor({s32, s64});
getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{s64, s32}});
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor({{s32, s64}});
computeTables(); computeTables();
verify(*ST.getInstrInfo()); verify(*ST.getInstrInfo());
} }
bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const { GISelChangeObserver &Observer) const {
using namespace TargetOpcode; using namespace TargetOpcode;
MIRBuilder.setInstr(MI); MIRBuilder.setInstr(MI);
return false; return false;
} }

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines case G_FCMP: {
const RegisterBankInfo::ValueMapping *FPRValueMapping = const RegisterBankInfo::ValueMapping *FPRValueMapping =
Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx]; : &Mips::ValueMappings[Mips::DPRIdx];
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
FPRValueMapping, FPRValueMapping}); FPRValueMapping, FPRValueMapping});
break; break;
} }
case G_FPEXT:
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
&Mips::ValueMappings[Mips::SPRIdx]});
break;
case G_FPTRUNC:
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
&Mips::ValueMappings[Mips::DPRIdx]});
break;
case G_CONSTANT: case G_CONSTANT:
case G_FRAME_INDEX: case G_FRAME_INDEX:
case G_GLOBAL_VALUE: case G_GLOBAL_VALUE:
case G_BRCOND: case G_BRCOND:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break; break;
case G_ICMP: case G_ICMP:
Show All 19 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
define void @fptrunc() {entry: ret void}
...
---
name: fpext
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fpext
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[CVT_D32_S:%[0-9]+]]:afgr64 = CVT_D32_S [[COPY]]
; FP32: $d0 = COPY [[CVT_D32_S]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fpext
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[CVT_D64_S:%[0-9]+]]:fgr64 = CVT_D64_S [[COPY]]
; FP64: $d0 = COPY [[CVT_D64_S]]
; FP64: RetRA implicit $d0
%0:fprb(s32) = COPY $f12
%1:fprb(s64) = G_FPEXT %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
...
---
name: fptrunc
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fptrunc
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[CVT_S_D32_:%[0-9]+]]:fgr32 = CVT_S_D32 [[COPY]]
; FP32: $f0 = COPY [[CVT_S_D32_]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fptrunc
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[CVT_S_D64_:%[0-9]+]]:fgr32 = CVT_S_D64 [[COPY]]
; FP64: $f0 = COPY [[CVT_S_D64_]]
; FP64: RetRA implicit $f0
%0:fprb(s64) = COPY $d6
%1:fprb(s32) = G_FPTRUNC %0(s64)
$f0 = COPY %1(s32)
RetRA implicit $f0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
define void @fptrunc() {entry: ret void}
...
---
name: fpext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fpext
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
; FP32: $d0 = COPY [[FPEXT]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fpext
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
; FP64: $d0 = COPY [[FPEXT]](s64)
; FP64: RetRA implicit $d0
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPEXT %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
...
---
name: fptrunc
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fptrunc
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)
; FP32: $f0 = COPY [[FPTRUNC]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fptrunc
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
; FP64: RetRA implicit $f0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTRUNC %0(s64)
$f0 = COPY %1(s32)
RetRA implicit $f0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
define double @fpext(float %a) {
; MIPS32-LABEL: fpext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: cvt.d.s $f0, $f12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fpext float %a to double
ret double %conv
}
define float @fptrunc(double %a) {
; MIPS32-LABEL: fptrunc:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: cvt.s.d $f0, $f12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptrunc double %a to float
ret float %conv
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
define void @fptrunc() {entry: ret void}
...
---
name: fpext
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fpext
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP32: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32)
; FP32: $d0 = COPY [[FPEXT]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fpext
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32)
; FP64: $d0 = COPY [[FPEXT]](s64)
; FP64: RetRA implicit $d0
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPEXT %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
...
---
name: fptrunc
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fptrunc
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP32: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64)
; FP32: $f0 = COPY [[FPTRUNC]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fptrunc
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
; FP64: RetRA implicit $f0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTRUNC %0(s64)
$f0 = COPY %1(s32)
RetRA implicit $f0
...