[AMDGPU] Added target feature +disable-form-clauses

[tpr]

Summary

With LLPC, previous investigation has suggested that si-scheduler
interacts badly with SiFormMemoryClauses on an XNACK target in some
games.

That needs further investigation in the future. In the meantime, this
commit adds a target feature to disable SIFormMemoryClauses on a
per-function basis for LLPC to use.

[rampitec]

Can we avoid negative (e.g. "disable") features?

[rampitec]

Actually it doesn't look like a feature at all. This is rather an option, which can also be set on a per-function basis. Also note, making it a feature will make it incompatible for inlining into parent and incompatible with any function which may be inlined into it.

[tpr]

V2: Target-specific attribute instead of target feature, as suggested by Stas.

[rampitec]

LGTM

llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
   MRI = &MF.getRegInfo();
   MFI = MF.getInfo<SIMachineFunctionInfo>();
   LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
   SlotIndexes *Ind = LIS->getSlotIndexes();
   bool Changed = false;
 
   MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
   MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();
+  unsigned FuncMaxClause = AMDGPU::getIntegerAttribute(
+      MF.getFunction(), "amdgpu-max-memory-clause", MaxClause);
 
   for (MachineBasicBlock &MBB : MF) {
     MachineBasicBlock::instr_iterator Next;
     for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; I = Next) {
       MachineInstr &MI = *I;
       Next = std::next(I);
 
       bool IsVMEM = isVMEMClauseInst(MI);
 
       if (!isValidClauseInst(MI, IsVMEM))
         continue;
 
       RegUse Defs, Uses;
       GCNDownwardRPTracker RPT(*LIS);
       RPT.reset(MI);
 
       if (!processRegUses(MI, Defs, Uses, RPT))
         continue;
 
       unsigned Length = 1;
-      for ( ; Next != E && Length < MaxClause; ++Next) {
+      for ( ; Next != E && Length < FuncMaxClause; ++Next) {
         if (!isValidClauseInst(*Next, IsVMEM))
           break;
 
         // A load from pointer which was loaded inside the same bundle is an
         // impossible clause because we will need to write and read the same
         // register inside. In this case processRegUses will return false.
         if (!processRegUses(*Next, Defs, Uses, RPT))
           break;

llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll

+; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}name:{{[  ]*}}vector_clause
+; GCN:      BUNDLE
+; GCN-NEXT: LOAD_DWORDX2
+; GCN-NEXT: LOAD_DWORDX2
+; GCN-NEXT: {{^ *[}]}}
+define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp2 = zext i32 %tmp to i64
+  %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
+  %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
+  %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
+  %tmp6 = add nuw nsw i64 %tmp2, 1
+  %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
+  %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
+  %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
+  %tmp10 = add nuw nsw i64 %tmp2, 2
+  %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
+  %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
+  %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
+  %tmp14 = add nuw nsw i64 %tmp2, 3
+  %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
+  %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
+  %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
+  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
+  store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
+  store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
+  store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
+  ret void
+}
+
+; GCN-LABEL: {{^}}name:{{[  ]*}}no_vector_clause
+; GCN-NOT:   BUNDLE
+define amdgpu_kernel void @no_vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) #0 {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp2 = zext i32 %tmp to i64
+  %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
+  %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
+  %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
+  %tmp6 = add nuw nsw i64 %tmp2, 1
+  %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
+  %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
+  %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
+  %tmp10 = add nuw nsw i64 %tmp2, 2
+  %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
+  %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
+  %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
+  %tmp14 = add nuw nsw i64 %tmp2, 3
+  %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
+  %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
+  %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
+  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
+  store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
+  store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
+  store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
+  ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
+
+attributes #0 = { "amdgpu-max-memory-clause"="1" }
+