[PowerPC] check for INLINEASM_BR along w/ INLINEASM

[nickdesaulniers]

Summary

It looks like since INLINEASM_BR was created off of INLINEASM (r353563),
a few checks for INLINEASM needed to be updated to check for either
case.

pr/41999

[hfinkel]

LGTM

[hfinkel]

In D62403#1516515, @hfinkel wrote:

LGTM

Also, I'm fine with these as by-inspection changes, but if there are reasonably-easy ways to write test cases (or update existing ones), please do.

[nickdesaulniers]

Also, I'm fine with these as by-inspection changes, but if there are reasonably-easy ways to write test cases (or update existing ones), please do.

Thank you for the review, and I understand. Short of writing a full on unit test (llvm/unittests/Target/PowerPC/testcase.cpp) I don't have a reproducer in hand nor know enough about PPC assembly to derive a test case that exposes the same issue as seen on arm. Maybe something where a large amount of inline asm in a callbr would prevent inlining, but even that is kind of brittle. Merging for now, but if you have more ideas I'm happy to commit tests after the fact.

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

 }
 
 /// GetInstSize - Return the number of bytes of code the specified
 /// instruction may be.  This returns the maximum number of bytes.
 ///
 unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   unsigned Opcode = MI.getOpcode();
 
-  if (Opcode == PPC::INLINEASM) {
+  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
     const MachineFunction *MF = MI.getParent()->getParent();
     const char *AsmStr = MI.getOperand(0).getSymbolName();
     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
   } else if (Opcode == TargetOpcode::STACKMAP) {
     StackMapOpers Opers(&MI);
     return Opers.getNumPatchBytes();
   } else if (Opcode == TargetOpcode::PATCHPOINT) {
     PatchPointOpers Opers(&MI);

llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

for (MachineInstr &MI : MBB) {
       // web will kill the optimization, at least for now.  For these
       // we do nothing, causing the optimization to fail.
       // FIXME: Some of these could be permitted with special handling,
       // and will be phased in as time permits.
       // FIXME: There is no simple and maintainable way to express a set
       // of opcodes having a common attribute in TableGen.  Should this
       // change, this is a prime candidate to use such a mechanism.
       case PPC::INLINEASM:
+      case PPC::INLINEASM_BR:
       case PPC::EXTRACT_SUBREG:
       case PPC::INSERT_SUBREG:
       case PPC::COPY_TO_REGCLASS:
       case PPC::LVEBX:
       case PPC::LVEHX:
       case PPC::LVEWX:
       case PPC::LVSL:
       case PPC::LVSR: