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Differential D61984

AMDGPU/GlobalISel: Legalize G_FCEIL
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Authored by arsenm on May 15 2019, 8:18 PM.

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rampitec
tstellar

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arsenm created this revision.May 15 2019, 8:18 PM
Herald added subscribers: Petar.Avramovic, t-tye, tpr and 8 others. · View Herald TranscriptMay 15 2019, 8:18 PM
tstellar accepted this revision.May 16 2019, 8:05 PM

LGTM.

This revision is now accepted and ready to land.May 16 2019, 8:05 PM
arsenm closed this revision.May 17 2019, 5:18 AM

r361028

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
37 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
275 lines

Diff 199726

lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Show All 34 Linespublic:
unsigned getSegmentAperture(unsigned AddrSpace, unsigned getSegmentAperture(unsigned AddrSpace,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const;
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
}; };
} // End llvm namespace. } // End llvm namespace.
#endif #endif

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalFor({{S32, S32}, {S32, S64}}) .legalFor({{S32, S32}, {S32, S64}})
.scalarize(0); .scalarize(0);
getActionDefinitionsBuilder(G_INTRINSIC_ROUND) getActionDefinitionsBuilder(G_INTRINSIC_ROUND)
.legalFor({S32, S64}) .legalFor({S32, S64})
.scalarize(0); .scalarize(0);
if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) { if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FRINT}) getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FCEIL, G_FRINT})
.legalFor({S32, S64}) .legalFor({S32, S64})
.clampScalar(0, S32, S64) .clampScalar(0, S32, S64)
.scalarize(0); .scalarize(0);
} else { } else {
getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FRINT}) getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FCEIL, G_FRINT})
.legalFor({S32}) .legalFor({S32})
.customFor({S64}) .customFor({S64})
.clampScalar(0, S32, S64) .clampScalar(0, S32, S64)
.scalarize(0); .scalarize(0);
} }
getActionDefinitionsBuilder(G_GEP) getActionDefinitionsBuilder(G_GEP)
.legalForCartesianProduct(AddrSpaces64, {S64}) .legalForCartesianProduct(AddrSpaces64, {S64})
▲ Show 20 Lines • Show All 373 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const { GISelChangeObserver &Observer) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case TargetOpcode::G_ADDRSPACE_CAST: case TargetOpcode::G_ADDRSPACE_CAST:
return legalizeAddrSpaceCast(MI, MRI, MIRBuilder); return legalizeAddrSpaceCast(MI, MRI, MIRBuilder);
case TargetOpcode::G_FRINT: case TargetOpcode::G_FRINT:
return legalizeFrint(MI, MRI, MIRBuilder); return legalizeFrint(MI, MRI, MIRBuilder);
case TargetOpcode::G_FCEIL:
return legalizeFceil(MI, MRI, MIRBuilder);
case TargetOpcode::G_INTRINSIC_TRUNC: case TargetOpcode::G_INTRINSIC_TRUNC:
return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder); return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder);
default: default:
return false; return false;
} }
llvm_unreachable("expected switch to return"); llvm_unreachable("expected switch to return");
} }
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeFrint(
auto C2 = MIRBuilder.buildFConstant(Ty, C2Val); auto C2 = MIRBuilder.buildFConstant(Ty, C2Val);
auto Fabs = MIRBuilder.buildFAbs(Ty, Src); auto Fabs = MIRBuilder.buildFAbs(Ty, Src);
auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2); auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
return true; return true;
} }
bool AMDGPULegalizerInfo::legalizeFceil(
MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
B.setInstr(MI);
unsigned Src = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(Src);
assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
// result = trunc(src)
// if (src > 0.0 && src != result)
// result += 1.0
LLT S1 = LLT::scalar(1);
LLT S64 = LLT::scalar(64);
auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
const auto Zero = B.buildFConstant(S64, 0.0);
const auto One = B.buildFConstant(S64, 1.0);
auto Lt0 = B.buildFCmp(CmpInst::FCMP_OGT, S1, Src, Zero);
auto NeTrunc = B.buildFCmp(CmpInst::FCMP_ONE, S1, Src, Trunc);
auto And = B.buildAnd(S1, Lt0, NeTrunc);
auto Add = B.buildSelect(S64, And, One, Zero);
// TODO: Should this propagate fast-math-flags?
B.buildFAdd(MI.getOperand(0).getReg(), Trunc, Add);
return true;
}
static MachineInstrBuilder extractF64Exponent(unsigned Hi, static MachineInstrBuilder extractF64Exponent(unsigned Hi,
MachineIRBuilder &B) { MachineIRBuilder &B) {
const unsigned FractBits = 52; const unsigned FractBits = 52;
const unsigned ExpBits = 11; const unsigned ExpBits = 11;
LLT S32 = LLT::scalar(32); LLT S32 = LLT::scalar(32);
auto Const0 = B.buildConstant(S32, FractBits - 32); auto Const0 = B.buildConstant(S32, FractBits - 32);
auto Const1 = B.buildConstant(S32, ExpBits); auto Const1 = B.buildConstant(S32, ExpBits);
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer -o - %s | FileCheck -check-prefix=CI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: test_fceil_s16
body: |
bb.0:
liveins: $vgpr0
; SI-LABEL: name: test_fceil_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; CI-LABEL: name: test_fceil_s16
; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; CI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_fceil_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
; VI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_fceil_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
; GFX9: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s16) = G_FCEIL %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_fceil_s32
body: |
bb.0:
liveins: $vgpr0
; SI-LABEL: name: test_fceil_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: $vgpr0 = COPY [[COPY]](s32)
; CI-LABEL: name: test_fceil_s32
; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CI: $vgpr0 = COPY [[COPY]](s32)
; VI-LABEL: name: test_fceil_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: $vgpr0 = COPY [[COPY]](s32)
; GFX9-LABEL: name: test_fceil_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
$vgpr0 = COPY %0
...
---
name: test_fceil_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_fceil_s64
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[INTRINSIC_TRUNC]]
; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
; SI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
; CI-LABEL: name: test_fceil_s64
; CI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
; CI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
; VI-LABEL: name: test_fceil_s64
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
; VI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
; GFX9-LABEL: name: test_fceil_s64
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
; GFX9: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_fceil_v2s16
body: |
bb.0:
liveins: $vgpr0
; SI-LABEL: name: test_fceil_v2s16
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
; CI-LABEL: name: test_fceil_v2s16
; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
; VI-LABEL: name: test_fceil_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: $vgpr0 = COPY [[COPY]](<2 x s16>)
; GFX9-LABEL: name: test_fceil_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: $vgpr0 = COPY [[COPY]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_FCEIL %0
$vgpr0 = COPY %0
...
---
name: test_fceil_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_fceil_v2s32
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CI-LABEL: name: test_fceil_v2s32
; CI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_fceil_v2s32
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
; VI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fceil_v2s32
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
; GFX9: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_fceil_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-LABEL: name: test_fceil_v2s64
; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[INTRINSIC_TRUNC]]
; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND3]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)
; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]
; SI: [[AND4:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]]
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT2]]
; SI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
; SI: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s64), [[C8]]
; SI: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[INTRINSIC_TRUNC1]]
; SI: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s1), [[C9]], [[C8]]
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT3]]
; SI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; CI-LABEL: name: test_fceil_v2s64
; CI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
; CI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; VI-LABEL: name: test_fceil_v2s64
; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
; VI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; GFX9-LABEL: name: test_fceil_v2s64
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
; GFX9: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = G_FCEIL %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...