gn build: Fewer dependencies in llvm/lib/Target

[thakis]

Summary

The tablegen groups only need public_deps for inc files included
(possibly transitively) in other targets. Move inc files that are
internan to the MCTargetDesc libraries into regular deps.

Reduces total size of the generated ninja files by 4kB and increases
build parallelism a tiny bit.

Related to the changes that merged InstPrinter into MCTargetDesc
(360484, 360486 etc).

[dlj]

Ah, this makes sense. I had missed the distinction on the :tablegen targets.

[thakis]

Thanks!

Landed in r360600, but forgot to add "Differential Revision:" line to commit message :/

llvm/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("AArch64GenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenAsmWriter1") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [
     "-gen-asm-writer",
     "-asmwriternum=1",
   ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenInstrInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-instr-info" ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenRegisterInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-register-info" ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../AArch64.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
     "../Utils",
   ]
   public_deps = [
-    ":AArch64GenAsmWriter",
-    ":AArch64GenAsmWriter1",
     ":AArch64GenInstrInfo",
-    ":AArch64GenMCCodeEmitter",
     ":AArch64GenRegisterInfo",
     ":AArch64GenSubtargetInfo",
   ]
 }
 
 static_library("MCTargetDesc") {
   output_name = "LLVMAArch64Desc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":AArch64GenAsmWriter",
+    ":AArch64GenAsmWriter1",
+    ":AArch64GenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/AArch64/TargetInfo",
     "//llvm/lib/Target/AArch64/Utils",
   ]
   include_dirs = [ ".." ]
   sources = [
     "AArch64AsmBackend.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("ARMGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../ARM.td"
 }
 
 tablegen("ARMGenInstrInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-instr-info" ]
   td_file = "../ARM.td"
 }
 
 tablegen("ARMGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../ARM.td"
 }
 
 tablegen("ARMGenRegisterInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-register-info" ]
   td_file = "../ARM.td"
 }
 
 tablegen("ARMGenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../ARM.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
     "../Utils",
   ]
   public_deps = [
-    ":ARMGenAsmWriter",
     ":ARMGenInstrInfo",
-    ":ARMGenMCCodeEmitter",
     ":ARMGenRegisterInfo",
     ":ARMGenSubtargetInfo",
   ]
 }
 static_library("MCTargetDesc") {
   output_name = "LLVMARMDesc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":ARMGenAsmWriter",
+    ":ARMGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Support",
     "//llvm/lib/Target/ARM/TargetInfo",
     "//llvm/lib/Target/ARM/Utils",
   ]
   include_dirs = [ ".." ]
   sources = [

llvm/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("BPFGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../BPF.td"
 }
 
 tablegen("BPFGenInstrInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-instr-info" ]
   td_file = "../BPF.td"
 }
 
 tablegen("BPFGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../BPF.td"
 }
 
 tablegen("BPFGenRegisterInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-register-info" ]
   td_file = "../BPF.td"
 }
 
 tablegen("BPFGenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../BPF.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
   ]
   public_deps = [
-    ":BPFGenAsmWriter",
     ":BPFGenInstrInfo",
-    ":BPFGenMCCodeEmitter",
     ":BPFGenRegisterInfo",
     ":BPFGenSubtargetInfo",
   ]
 }
 
 static_library("MCTargetDesc") {
   output_name = "LLVMBPFDesc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":BPFGenAsmWriter",
+    ":BPFGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Support",
     "//llvm/lib/Target/BPF/TargetInfo",
   ]
   include_dirs = [ ".." ]
   sources = [
     "BPFAsmBackend.cpp",
     "BPFELFObjectWriter.cpp",
     "BPFInstPrinter.cpp",
     "BPFMCCodeEmitter.cpp",
     "BPFMCTargetDesc.cpp",
   ]
 }

llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("PPCGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../PPC.td"
 }
 
 tablegen("PPCGenInstrInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-instr-info" ]
   td_file = "../PPC.td"
 }
 
 tablegen("PPCGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../PPC.td"
 }
 
 tablegen("PPCGenRegisterInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-register-info" ]
   td_file = "../PPC.td"
 }
 
 tablegen("PPCGenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../PPC.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../InstPrinter",
     "../TargetInfo",
   ]
   public_deps = [
-    ":PPCGenAsmWriter",
     ":PPCGenInstrInfo",
-    ":PPCGenMCCodeEmitter",
     ":PPCGenRegisterInfo",
     ":PPCGenSubtargetInfo",
   ]
 }
 
 static_library("MCTargetDesc") {
   output_name = "LLVMPowerPCDesc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":PPCGenAsmWriter",
+    ":PPCGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/PowerPC/TargetInfo",
   ]
   include_dirs = [ ".." ]
   sources = [
     "PPCAsmBackend.cpp",
     "PPCELFObjectWriter.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("WebAssemblyGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../WebAssembly.td"
 }
 
 tablegen("WebAssemblyGenInstrInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-instr-info" ]
   td_file = "../WebAssembly.td"
 }
 
 tablegen("WebAssemblyGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../WebAssembly.td"
 }
 
 tablegen("WebAssemblyGenRegisterInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-register-info" ]
   td_file = "../WebAssembly.td"
 }
 
 tablegen("WebAssemblyGenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../WebAssembly.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../InstPrinter",
     "../TargetInfo",
     "../Utils",
   ]
   public_deps = [
-    ":WebAssemblyGenAsmWriter",
     ":WebAssemblyGenInstrInfo",
-    ":WebAssemblyGenMCCodeEmitter",
     ":WebAssemblyGenRegisterInfo",
     ":WebAssemblyGenSubtargetInfo",
   ]
 }
 static_library("MCTargetDesc") {
   output_name = "LLVMWebAssemblyDesc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":WebAssemblyGenAsmWriter",
+    ":WebAssemblyGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/WebAssembly/TargetInfo",
   ]
   include_dirs = [ ".." ]
   sources = [
     "WebAssemblyAsmBackend.cpp",
     "WebAssemblyInstPrinter.cpp",
     "WebAssemblyMCAsmInfo.cpp",
     "WebAssemblyMCCodeEmitter.cpp",
     "WebAssemblyMCTargetDesc.cpp",
     "WebAssemblyTargetStreamer.cpp",
     "WebAssemblyWasmObjectWriter.cpp",
   ]
 }

llvm/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("X86GenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../X86.td"
 }
 
 tablegen("X86GenAsmWriter1") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [
     "-gen-asm-writer",
     "-asmwriternum=1",
   ]
   td_file = "../X86.td"
 }
 
 tablegen("X86GenInstrInfo") {

 }
 
 tablegen("X86GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
   args = [ "-gen-subtarget" ]
   td_file = "../X86.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
   ]
   public_deps = [
-    ":X86GenAsmWriter",
-    ":X86GenAsmWriter1",
     ":X86GenInstrInfo",
     ":X86GenRegisterInfo",
     ":X86GenSubtargetInfo",
   ]
 }
 
 static_library("MCTargetDesc") {
   output_name = "LLVMX86Desc"
   public_deps = [
     ":tablegen",
   ]
   deps = [
+    ":X86GenAsmWriter",
+    ":X86GenAsmWriter1",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Object",
     "//llvm/lib/Support",
     "//llvm/lib/Target/X86/TargetInfo",
     "//llvm/lib/Target/X86/Utils",
   ]
   include_dirs = [ ".." ]