This is addition to r216371 (SLP and Loop Vectorization) and r218607 where
cost model for signed division by power of 2 was improved for AArch64.
The revision r218607 missed test case for Loop Vectorization.
Adding it here.
Please help in reviewing this patch. I will commit it after the review.
Regards,
Suyog
I'd prefer a space between the semicolon and the CHECK directive.