AMDGPU] Pattern for v_xor3_b32

[rampitec]

Summary

This also allows three op patterns to use increased constant bus
limit of GFX10.

[kzhuravl]

LGTM

lib/Target/AMDGPU/VOP3Instructions.td

[{
     //
     // Note: Use !isDivergent as a conservative proxy for whether the value
     //       is in an SGPR (uniform values can end up in VGPRs as well).
     unsigned ConstantBusUses = 0;
     for (unsigned i = 0; i < 3; ++i) {
       if (!Operands[i]->isDivergent() &&
           !isInlineImmediate(Operands[i].getNode())) {
         ConstantBusUses++;
-        if (ConstantBusUses >= 2)
+        // This uses AMDGPU::V_ADD3_U32, but all three operand instructions
+        // have the same constant bus limit.
+        if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32))
           return false;
       }
     }
 
     return true;
   }]
 > {
   let PredicateCodeUsesOperands = 1;

 def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>;
 def : ThreeOp_i32_Pats<or, or, V_OR3_B32>;
 def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;
 
 } // End SubtargetPredicate = isGFX9Plus
 
 let SubtargetPredicate = isGFX10Plus in {
   def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
+  def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>;
 } // End SubtargetPredicate = isGFX10Plus
 
 //===----------------------------------------------------------------------===//
 // Integer Clamp Patterns
 //===----------------------------------------------------------------------===//
 
 class getClampPat<VOPProfile P, SDPatternOperator node> {
   dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));

test/CodeGen/AMDGPU/add3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_ADD3_U32
 ; ===================================================================================
 
 define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: add3:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; V_MAD_U32_U24 is given higher priority.
 define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
 ; VI-LABEL: mad_no_add3:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
 ; VI-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: mad_no_add3:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
 ; GFX9-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: mad_no_add3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_mad_u32_u24 v0, v0, v1, v4
+; GFX10-NEXT:    v_mad_u32_u24 v0, v2, v3, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %a0 = shl i32 %a, 8
   %a1 = lshr i32 %a0, 8
   %b0 = shl i32 %b, 8
   %b1 = lshr i32 %b0, 8
   %mul1 = mul i32 %a1, %b1
 
   %c0 = shl i32 %c, 8
   %c1 = lshr i32 %c0, 8

 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_vgpr_b:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_add_i32 s3, s3, s2
 ; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, s3, s2, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: add3_vgpr_all2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_vgpr_all2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add3_u32 v0, v1, v2, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_all2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, v1, v2, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %b, %c
   %result = add i32 %a, %x
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
 ; VI-LABEL: add3_vgpr_bc:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_vgpr_bc:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add3_u32 v0, s2, v0, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_bc:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, s2, v0, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: add3_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 16, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add3_u32 v0, v0, v1, 16
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, v0, v1, 16
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = add i32 %x, 16
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
 ; VI-LABEL: add3_multiuse_outer:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    v_mul_lo_u32 v1, v0, v3
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_multiuse_outer:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v3
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_multiuse_outer:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    v_mul_lo_u32 v1, v0, v3
+; GFX10-NEXT:    ; return to shader part epilog
   %inner = add i32 %a, %b
   %outer = add i32 %inner, %c
   %x1 = mul i32 %outer, %x
   %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
   %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
   %bc = bitcast <2 x i32> %r0 to <2 x float>
   ret <2 x float> %bc
 }
 
 define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: add3_multiuse_inner:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add3_multiuse_inner:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_add_u32_e32 v1, v0, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_multiuse_inner:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v0, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %inner = add i32 %a, %b
   %outer = add i32 %inner, %c
   %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
   %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
   %bc = bitcast <2 x i32> %r0 to <2 x float>
   ret <2 x float> %bc
 }
 

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0x40400000
 ; GFX9-NEXT:    v_add_f32_e64 v0, s2, 1.0
 ; GFX9-NEXT:    v_add_f32_e64 v1, s3, 2.0
 ; GFX9-NEXT:    v_add_f32_e32 v2, s4, v2
 ; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add3_uniform_vgpr:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_f32_e64 v1, s3, 2.0
+; GFX10-NEXT:    v_add_f32_e64 v2, s2, 1.0
+; GFX10-NEXT:    v_add_f32_e64 v0, 0x40400000, s4
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v1, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %a1 = fadd float %a, 1.0
   %b2 = fadd float %b, 2.0
   %c3 = fadd float %c, 3.0
   %bc.a = bitcast float %a1 to i32
   %bc.b = bitcast float %b2 to i32
   %bc.c = bitcast float %c3 to i32
   %x = add i32 %bc.a, %bc.b
   %result = add i32 %x, %bc.c
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/add_shl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_ADD_LSHL_U32
 ; ===================================================================================
 
 define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: add_shl:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_lshl_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = shl i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
 ; VI-LABEL: add_shl_vgpr_c:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_add_i32 s2, s2, s3
 ; VI-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl_vgpr_c:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_add_i32 s2, s2, s3
 ; GFX9-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl_vgpr_c:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_lshl_u32 v0, s2, s3, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = shl i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
 ; VI-LABEL: add_shl_vgpr_ac:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl_vgpr_ac:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_lshl_u32 v0, v0, s2, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl_vgpr_ac:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_lshl_u32 v0, v0, s2, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = shl i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: add_shl_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, 9
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_lshl_u32 v0, v0, v1, 9
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, %b
   %result = shl i32 %x, 9
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
 ; VI-LABEL: add_shl_vgpr_const_inline_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x7e800, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl_vgpr_const_inline_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7e800
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl_vgpr_const_inline_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 9, 0x7e800
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, 1012
   %result = shl i32 %x, 9
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; TODO: Non-optimal code generation because SelectionDAG combines
 ;       (shl (add x, CONST), y) ---> (add (shl x, y), CONST').
 ;
 define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
 ; VI-LABEL: add_shl_vgpr_inline_const_x2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x600, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: add_shl_vgpr_inline_const_x2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x600
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: add_shl_vgpr_inline_const_x2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 9, 0x600
+; GFX10-NEXT:    ; return to shader part epilog
   %x = add i32 %a, 3
   %result = shl i32 %x, 9
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/and_or.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_AND_OR_B32
 ; ===================================================================================
 
 define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: and_or:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
 define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
 ; VI-LABEL: and_or_vgpr_b:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_or_b32_e32 v0, s3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or_vgpr_b:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
 ; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s3
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
 ; VI-LABEL: and_or_vgpr_ab:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_or_b32_e32 v0, s2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or_vgpr_ab:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_ab:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, s2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: and_or_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, 4, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 4, %a
   %result = or i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
 ; VI-LABEL: and_or_vgpr_const_inline_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, 20, v0
 ; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or_vgpr_const_inline_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_const_inline_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 20, 0x808
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 20, %a
   %result = or i32 %x, 2056
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
 ; VI-LABEL: and_or_vgpr_inline_const_x2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_and_b32_e32 v0, 4, v0
 ; VI-NEXT:    v_or_b32_e32 v0, 1, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: and_or_vgpr_inline_const_x2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_inline_const_x2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, 1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 4, %a
   %result = or i32 %x, 1
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/or3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_OR3_B32
 ; ===================================================================================
 
 define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: or3:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: or3:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: or3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
 ; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b32
 define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
 ; VI-LABEL: or3_vgpr_a:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_or_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_or_b32_e32 v0, s3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: or3_vgpr_a:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
 ; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: or3_vgpr_a:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v0, s2, s3
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: or3_vgpr_all2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v2
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: or3_vgpr_all2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: or3_vgpr_all2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or i32 %b, %c
   %result = or i32 %a, %x
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
 ; VI-LABEL: or3_vgpr_bc:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_or_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: or3_vgpr_bc:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_or3_b32 v0, s2, v0, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: or3_vgpr_bc:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, s2, v0, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: or3_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_or_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_or_b32_e32 v0, 64, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: or3_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_or3_b32 v0, v1, v0, 64
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: or3_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v1, v0, 64
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or i32 64, %b
   %result = or i32 %x, %a
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/shl_add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_LSHL_ADD_U32
 ; ===================================================================================
 
 define amdgpu_ps float @shl_add(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: shl_add:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_add:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_add:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
 define amdgpu_ps float @shl_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
 ; VI-LABEL: shl_add_vgpr_a:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_add_vgpr_a:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
 ; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_add_vgpr_a:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, s2, s3
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: shl_add_vgpr_all:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_add_vgpr_all:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_add_vgpr_all:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
 ; VI-LABEL: shl_add_vgpr_ab:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_add_vgpr_ab:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_add_vgpr_ab:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, s2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_add_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: shl_add_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_add_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_add_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 3, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, 3
   %result = add i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/shl_or.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_LSHL_OR_B32
 ; ===================================================================================
 
 define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: shl_or:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
 ; VI-LABEL: shl_or_vgpr_c:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_lshl_b32 s0, s2, s3
 ; VI-NEXT:    v_or_b32_e32 v0, s0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_c:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_lshl_b32 s0, s2, s3
 ; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_c:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, s2, s3, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: shl_or_vgpr_all2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_all2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_all2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = or i32 %c, %x
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
 ; VI-LABEL: shl_or_vgpr_ac:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_ac:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_ac:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: shl_or_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
 ; VI-NEXT:    v_or_b32_e32 v0, 6, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, %b
   %result = or i32 %x, 6
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
 ; VI-LABEL: shl_or_vgpr_const2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_const2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_const2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, 6
   %result = or i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
 ; VI-LABEL: shl_or_vgpr_const_scalar1:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_lshl_b32 s0, s2, 6
 ; VI-NEXT:    v_or_b32_e32 v0, s0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_const_scalar1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_const_scalar1:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, 6
   %result = or i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
 ; VI-LABEL: shl_or_vgpr_const_scalar2:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
 ; VI-NEXT:    v_or_b32_e32 v0, s2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: shl_or_vgpr_const_scalar2:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: shl_or_vgpr_const_scalar2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = shl i32 %a, 6
   %result = or i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }

test/CodeGen/AMDGPU/xor3.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
+
+; ===================================================================================
+; V_XOR3_B32
+; ===================================================================================
+
+define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) {
+; GFX9-LABEL: xor3:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = xor i32 %a, %b
+  %result = xor i32 %x, %c
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}
+
+define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
+; GFX9-LABEL: xor3_vgpr_b:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT:    v_xor_b32_e32 v0, s3, v0
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_vgpr_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, s2, v0, s3
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = xor i32 %a, %b
+  %result = xor i32 %x, %c
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}
+
+define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
+; GFX9-LABEL: xor3_vgpr_all2:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_vgpr_all2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, v1, v2, v0
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = xor i32 %b, %c
+  %result = xor i32 %a, %x
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}
+
+define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
+; GFX9-LABEL: xor3_vgpr_bc:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_vgpr_bc:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, s2, v0, v1
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = xor i32 %a, %b
+  %result = xor i32 %x, %c
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}
+
+define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) {
+; GFX9-LABEL: xor3_vgpr_const:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_xor_b32_e32 v0, 16, v0
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, v0, v1, 16
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = xor i32 %a, %b
+  %result = xor i32 %x, 16
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}
+
+define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
+; GFX9-LABEL: xor3_multiuse_outer:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v3
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_multiuse_outer:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor3_b32 v0, v0, v1, v2
+; GFX10-NEXT:    v_mul_lo_u32 v1, v0, v3
+; GFX10-NEXT:    ; return to shader part epilog
+  %inner = xor i32 %a, %b
+  %outer = xor i32 %inner, %c
+  %x1 = mul i32 %outer, %x
+  %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
+  %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
+  %bc = bitcast <2 x i32> %r0 to <2 x float>
+  ret <2 x float> %bc
+}
+
+define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
+; GFX9-LABEL: xor3_multiuse_inner:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_xor_b32_e32 v1, v0, v2
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_multiuse_inner:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX10-NEXT:    v_xor_b32_e32 v1, v0, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %inner = xor i32 %a, %b
+  %outer = xor i32 %inner, %c
+  %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
+  %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
+  %bc = bitcast <2 x i32> %r0 to <2 x float>
+  ret <2 x float> %bc
+}
+
+; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here,
+; but we don't.
+define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
+; GFX9-LABEL: xor3_uniform_vgpr:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x40400000
+; GFX9-NEXT:    v_add_f32_e64 v0, s2, 1.0
+; GFX9-NEXT:    v_add_f32_e64 v1, s3, 2.0
+; GFX9-NEXT:    v_add_f32_e32 v2, s4, v2
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor3_uniform_vgpr:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_f32_e64 v1, s3, 2.0
+; GFX10-NEXT:    v_add_f32_e64 v2, s2, 1.0
+; GFX10-NEXT:    v_add_f32_e64 v0, 0x40400000, s4
+; GFX10-NEXT:    v_xor_b32_e32 v1, v2, v1
+; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT:    ; return to shader part epilog
+  %a1 = fadd float %a, 1.0
+  %b2 = fadd float %b, 2.0
+  %c3 = fadd float %c, 3.0
+  %bc.a = bitcast float %a1 to i32
+  %bc.b = bitcast float %b2 to i32
+  %bc.c = bitcast float %c3 to i32
+  %x = xor i32 %bc.a, %bc.b
+  %result = xor i32 %x, %bc.c
+  %bc = bitcast i32 %result to float
+  ret float %bc
+}

test/CodeGen/AMDGPU/xor_add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_XAD_U32
 ; ===================================================================================
 
 define amdgpu_ps float @xor_add(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: xor_add:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: xor_add:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_xad_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor_add:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xad_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = xor i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
 define amdgpu_ps float @xor_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
 ; VI-LABEL: xor_add_vgpr_a:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_xor_b32_e32 v0, s2, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: xor_add_vgpr_a:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
 ; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor_add_vgpr_a:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xad_u32 v0, v0, s2, s3
+; GFX10-NEXT:    ; return to shader part epilog
   %x = xor i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @xor_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
 ; VI-LABEL: xor_add_vgpr_all:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: xor_add_vgpr_all:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_xad_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor_add_vgpr_all:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xad_u32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = xor i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @xor_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
 ; VI-LABEL: xor_add_vgpr_ab:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: xor_add_vgpr_ab:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_xad_u32 v0, v0, v1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor_add_vgpr_ab:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xad_u32 v0, v0, v1, s2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = xor i32 %a, %b
   %result = add i32 %x, %c
   %bc = bitcast i32 %result to float
   ret float %bc
 }
 
 define amdgpu_ps float @xor_add_vgpr_const(i32 %a, i32 %b) {
 ; VI-LABEL: xor_add_vgpr_const:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_xor_b32_e32 v0, 3, v0
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: xor_add_vgpr_const:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_xad_u32 v0, v0, 3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: xor_add_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_xad_u32 v0, v0, 3, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = xor i32 %a, 3
   %result = add i32 %x, %b
   %bc = bitcast i32 %result to float
   ret float %bc
 }