This fixes case where one could have LE(A, B) AND LE(B, A) for different sized
vector types A,B.
Details
- Reviewers
kparzysz - Commits
- rZORGcccd29849feb: [TableGen] - Type comparison LE should be LT or equal.
rGcccd29849feb: [TableGen] - Type comparison LE should be LT or equal.
rG380eaa0cfabe: [TableGen] - Type comparison LE should be LT or equal.
rL361183: [TableGen] - Type comparison LE should be LT or equal.
Diff Detail
- Repository
- rG LLVM Github Monorepo
- Build Status
Buildable 31645 Build 31644: arc lint + arc unit
Event Timeline
llvm/utils/TableGen/CodeGenDAGPatterns.cpp | ||
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517 | Krzysztof, I believe you made this change? I was not able to find these trunc patterns in the X86 backend, and all the default backends seem to build/test fine with my change here. Can you comment on whether this looks OK to you? |
The X86 patterns are probably heavily hidden in tablegen classes, but they should be easily visible in X86GenDAGISel.inc. Does that file generate the same before and after this change?
/*515111*/ /*Scope*/ 26, /*->515138*/ /*515112*/ OPC_CheckChild0Type, MVT::v4i32, /*515114*/ OPC_SwitchType /*2 cases */, 9, MVT::v16i8,// ->515126 /*515117*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasAVX512()) && (Subtarget->hasVLX()) /*515119*/ OPC_MorphNodeTo1, TARGET_VAL(X86::VPMOVDBZ128rr), 0, MVT::v16i8, 1/*#Ops*/, 0,· // Src: (X86vtrunc:{ *:[v16i8] } VR128X:{ *:[v4i32] }:$src) - Complexity = 3 // Dst: (VPMOVDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v4i32] }:$src)
llvm/utils/TableGen/CodeGenDAGPatterns.cpp | ||
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517 | I think it was originally < or ==, but then I encountered those issues in the x86 backend, so I changed it to <. In any case, the original intent was <=, so if it works now, I'm fine with it. |
Krzysztof, I believe you made this change? I was not able to find these trunc patterns in the X86 backend, and all the default backends seem to build/test fine with my change here. Can you comment on whether this looks OK to you?