[SimplifyCFG] NFC, update Switch tests to HEAD so I can see if my changes change anything

[shawnl]

Summary

I am trying to move towards much more space-efficient switch statements, using popcnt, as described in PR39013. This is the first in a series.

Also add baseline tests to show effect of later patches.

The previous version of this patch series: D61150

[shawnl]

include more tests

[shawnl]

I was confused because the disable-lookup-table.ll not having a datalayout was causing problems.

[nikic]

test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll

8–9

Here and in the next file: You've generated new CHECK lines with update_test_checks, but the old ones are still there. These need to be manually dropped.

test/Transforms/SimplifyCFG/switch-dead-default.ll

2

Why the addition of -O3 here? Generally tests in test/SimplifyCFG should use only -simplifycfg.

[jmolloy]

LGTM.

test/Transforms/SimplifyCFG/X86/lit.local.cfg

1 ↗

(On Diff #196734)

Revert hunk in this file.

[shawnl]

I will look into the issues nikic brought up

[nikic]

test/Transforms/SimplifyCFG/X86/lit.local.cfg

1 ↗

(On Diff #196734)

This one is not done yet.

test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll

375

A leftover CHECK.

1589

Leftover CHECK.

1676

Leftover CHECKs.

test/Transforms/SimplifyCFG/switch_create-custom-dl.ll

58

It looks like these check lines were added with an incorrect prefix originally and didn't do anything... They can be dropped now that the proper CHECKs are there.

89

Same here.

752

Leftover CHECKs.

816

Leftover CHECKS.

848

Leftover CHECKS.

test/Transforms/SimplifyCFG/switch_create.ll

742

Leftover CHECKS. (Also in the rest of this file.)

[nikic]

Still needs some duplicates CHECKs removed, per comments above.

[shawnl]

review. Also update a few more tests.

[nikic]

A few last issues...

test/Transforms/SimplifyCFG/switch-dead-default.ll

246

This seems odd. Are you sure these are the results without any other patches?

test/Transforms/SimplifyCFG/switch-on-const-select.ll

157–158

Does this test actually pass after being regenerated? I'd expect an error due to the undefined variable here. This probably needs to be replaced with just #0 if you're using it above.

test/Transforms/SimplifyCFG/switch_create-custom-dl.ll

763

More leftovers.

test/Transforms/SimplifyCFG/switch_create.ll

739

A few more left here...

[shawnl]

I'll get rid of the leftovers.

test/Transforms/SimplifyCFG/switch-on-const-select.ll

157–158

You are referring to the other file, but yes it fails, but no, this is not a bug in LLVM, but rather a bug in the test.

[shawnl]

comment didn't get included.

test/Transforms/SimplifyCFG/switch-dead-default.ll

246

Yes, and it is correct. I opened a bug and then was corrected that this is correct. Here is the patch removing this buggy test. https://reviews.llvm.org/D60859

[nikic]

test/Transforms/SimplifyCFG/switch-on-const-select.ll

157–158

I'm referring to the use of [[$NUW]] here, even though the corresponding [[$NUW:#[0-9]+]] above has been removed.

[shawnl]

remove line nikic mentioned

[shawnl]

applied 361725

test/Transforms/SimplifyCFG/ARM/cttz-ctlz.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -mtriple=arm -mattr=+v6t2 < %s | FileCheck %s
 
 define i32 @ctlz(i32 %A) {
 ; CHECK-LABEL: @ctlz(
-; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
-; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
-; CHECK-NEXT: ret i32 [[SEL]]
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[A]], i1 true)
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+;
 entry:
   %tobool = icmp eq i32 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:

   ret i32 %cond
 }
 
 define i32 @cttz(i32 %A) {
 ; CHECK-LABEL: @cttz(
-; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
-; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
-; CHECK-NEXT: ret i32 [[SEL]]
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[A]], i1 true)
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+;
 entry:
   %tobool = icmp eq i32 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:

test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ;RUN: opt -S -simplifycfg -mtriple=arm < %s | FileCheck %s
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 
-; CHECK-LABEL: select_trunc_i64
-; CHECK-NOT: br
-; CHECK: select
-; CHECK: select
 define arm_aapcscc i32 @select_trunc_i64(i32 %a, i32 %b) {
+; CHECK-LABEL: @select_trunc_i64(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
+; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[ADD]], 2147483647
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i64 [[ADD]], -2147483648
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TMP0]], i64 [[ADD]], i64 -2147483648
+; CHECK-NEXT:    [[EXTRACT_T:%.*]] = trunc i64 [[COND]] to i32
+; CHECK-NEXT:    [[COND8_OFF0:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[EXTRACT_T]]
+; CHECK-NEXT:    ret i32 [[COND8_OFF0]]
+;
 entry:
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
   %add = add nsw i64 %conv1, %conv
   %cmp = icmp sgt i64 %add, 2147483647

test/Transforms/SimplifyCFG/ARM/switch-to-lookup-table-constant-expr.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv7a--none-eabi"
 

 @g2 = external global i32, align 4
 @g3 = external global i32, align 4
 @g4 = external thread_local global i32, align 4
 
 define i32* @test3(i32 %n) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[N:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32* [ @g4, [[SW_DEFAULT]] ], [ getelementptr inbounds (i32, i32* inttoptr (i32 mul (i32 ptrtoint (i32* @g3 to i32), i32 2) to i32*), i32 1), [[SW_BB2]] ], [ @g2, [[SW_BB1]] ], [ @g1, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32* [[RETVAL_0]]
+;
 entry:
   switch i32 %n, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 
 sw.bb:
   br label %return
 

test/Transforms/SimplifyCFG/ARM/switch-to-lookup-table.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -switch-to-lookup -mtriple=arm -relocation-model=static    < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
 ; RUN: opt -S -simplifycfg -switch-to-lookup -mtriple=arm -relocation-model=pic       < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
 ; RUN: opt -S -simplifycfg -switch-to-lookup -mtriple=arm -relocation-model=ropi      < %s | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
 ; RUN: opt -S -simplifycfg -switch-to-lookup -mtriple=arm -relocation-model=rwpi      < %s | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
 ; RUN: opt -S -simplifycfg -switch-to-lookup -mtriple=arm -relocation-model=ropi-rwpi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE

 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv7a--none-eabi"
 
 define i32 @test1(i32 %n) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[N:%.*]], 3
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* @switch.table.test1, i32 0, i32 [[N]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 15498
+;
 entry:
   switch i32 %n, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 
 sw.bb:
   br label %return
 

 @c3 = external constant i32, align 4
 @c4 = external constant i32, align 4
 
 
 define i32* @test2(i32 %n) {
+; ENABLE-LABEL: @test2(
+; ENABLE-NEXT:  entry:
+; ENABLE-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[N:%.*]], 3
+; ENABLE-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; ENABLE:       switch.lookup:
+; ENABLE-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32*], [3 x i32*]* @switch.table.test2, i32 0, i32 [[N]]
+; ENABLE-NEXT:    [[SWITCH_LOAD:%.*]] = load i32*, i32** [[SWITCH_GEP]]
+; ENABLE-NEXT:    ret i32* [[SWITCH_LOAD]]
+; ENABLE:       return:
+; ENABLE-NEXT:    ret i32* @c4
+;
+; DISABLE-LABEL: @test2(
+; DISABLE-NEXT:  entry:
+; DISABLE-NEXT:    switch i32 [[N:%.*]], label [[SW_DEFAULT:%.*]] [
+; DISABLE-NEXT:    i32 0, label [[RETURN:%.*]]
+; DISABLE-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; DISABLE-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; DISABLE-NEXT:    ]
+; DISABLE:       sw.bb1:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       sw.bb2:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       sw.default:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       return:
+; DISABLE-NEXT:    [[RETVAL_0:%.*]] = phi i32* [ @c4, [[SW_DEFAULT]] ], [ @c3, [[SW_BB2]] ], [ @c2, [[SW_BB1]] ], [ @c1, [[ENTRY:%.*]] ]
+; DISABLE-NEXT:    ret i32* [[RETVAL_0]]
+;
 entry:
   switch i32 %n, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 
 sw.bb:
   br label %return
 

 @g2 = external global i32, align 4
 @g3 = external global i32, align 4
 @g4 = external global i32, align 4
 
 define i32* @test3(i32 %n) {
+; ENABLE-LABEL: @test3(
+; ENABLE-NEXT:  entry:
+; ENABLE-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[N:%.*]], 3
+; ENABLE-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; ENABLE:       switch.lookup:
+; ENABLE-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32*], [3 x i32*]* @switch.table.test3, i32 0, i32 [[N]]
+; ENABLE-NEXT:    [[SWITCH_LOAD:%.*]] = load i32*, i32** [[SWITCH_GEP]]
+; ENABLE-NEXT:    ret i32* [[SWITCH_LOAD]]
+; ENABLE:       return:
+; ENABLE-NEXT:    ret i32* @g4
+;
+; DISABLE-LABEL: @test3(
+; DISABLE-NEXT:  entry:
+; DISABLE-NEXT:    switch i32 [[N:%.*]], label [[SW_DEFAULT:%.*]] [
+; DISABLE-NEXT:    i32 0, label [[RETURN:%.*]]
+; DISABLE-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; DISABLE-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; DISABLE-NEXT:    ]
+; DISABLE:       sw.bb1:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       sw.bb2:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       sw.default:
+; DISABLE-NEXT:    br label [[RETURN]]
+; DISABLE:       return:
+; DISABLE-NEXT:    [[RETVAL_0:%.*]] = phi i32* [ @g4, [[SW_DEFAULT]] ], [ @g3, [[SW_BB2]] ], [ @g2, [[SW_BB1]] ], [ @g1, [[ENTRY:%.*]] ]
+; DISABLE-NEXT:    ret i32* [[RETVAL_0]]
+;
 entry:
   switch i32 %n, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 
 sw.bb:
   br label %return
 

 declare i32 @f3(i32, i32)
 declare i32 @f4(i32, i32)
 declare i32 @f5(i32, i32)
 
 define i32 @test4(i32 %a, i32 %b, i32 %c) {
+; ENABLE-LABEL: @test4(
+; ENABLE-NEXT:  entry:
+; ENABLE-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[A:%.*]], 1
+; ENABLE-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 3
+; ENABLE-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COND_FALSE6:%.*]]
+; ENABLE:       cond.false6:
+; ENABLE-NEXT:    [[CMP7:%.*]] = icmp eq i32 [[A]], 4
+; ENABLE-NEXT:    [[COND:%.*]] = select i1 [[CMP7]], i32 (i32, i32)* @f4, i32 (i32, i32)* @f5
+; ENABLE-NEXT:    br label [[COND_END11:%.*]]
+; ENABLE:       switch.lookup:
+; ENABLE-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32 (i32, i32)*], [3 x i32 (i32, i32)*]* @switch.table.test4, i32 0, i32 [[SWITCH_TABLEIDX]]
+; ENABLE-NEXT:    [[SWITCH_LOAD:%.*]] = load i32 (i32, i32)*, i32 (i32, i32)** [[SWITCH_GEP]]
+; ENABLE-NEXT:    br label [[COND_END11]]
+; ENABLE:       cond.end11:
+; ENABLE-NEXT:    [[COND12:%.*]] = phi i32 (i32, i32)* [ [[COND]], [[COND_FALSE6]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ]
+; ENABLE-NEXT:    [[CALL:%.*]] = call i32 [[COND12]](i32 [[B:%.*]], i32 [[C:%.*]])
+; ENABLE-NEXT:    ret i32 [[CALL]]
+;
+; DISABLE-LABEL: @test4(
+; DISABLE-NEXT:  entry:
+; DISABLE-NEXT:    switch i32 [[A:%.*]], label [[COND_FALSE6:%.*]] [
+; DISABLE-NEXT:    i32 1, label [[COND_END11:%.*]]
+; DISABLE-NEXT:    i32 2, label [[COND_END11_FOLD_SPLIT:%.*]]
+; DISABLE-NEXT:    i32 3, label [[COND_END11_FOLD_SPLIT1:%.*]]
+; DISABLE-NEXT:    ]
+; DISABLE:       cond.false6:
+; DISABLE-NEXT:    [[CMP7:%.*]] = icmp eq i32 [[A]], 4
+; DISABLE-NEXT:    [[COND:%.*]] = select i1 [[CMP7]], i32 (i32, i32)* @f4, i32 (i32, i32)* @f5
+; DISABLE-NEXT:    br label [[COND_END11]]
+; DISABLE:       cond.end11.fold.split:
+; DISABLE-NEXT:    br label [[COND_END11]]
+; DISABLE:       cond.end11.fold.split1:
+; DISABLE-NEXT:    br label [[COND_END11]]
+; DISABLE:       cond.end11:
+; DISABLE-NEXT:    [[COND12:%.*]] = phi i32 (i32, i32)* [ @f1, [[ENTRY:%.*]] ], [ [[COND]], [[COND_FALSE6]] ], [ @f2, [[COND_END11_FOLD_SPLIT]] ], [ @f3, [[COND_END11_FOLD_SPLIT1]] ]
+; DISABLE-NEXT:    [[CALL:%.*]] = call i32 [[COND12]](i32 [[B:%.*]], i32 [[C:%.*]])
+; DISABLE-NEXT:    ret i32 [[CALL]]
+;
 entry:
   %cmp = icmp eq i32 %a, 1
   br i1 %cmp, label %cond.end11, label %cond.false
 
 cond.false:

test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -switch-to-lookup -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 ; RUN: opt < %s -passes='simplify-cfg<switch-to-lookup>' -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 ; In the presence of "-no-jump-tables"="true", simplifycfg should not convert switches to lookup tables.
 
 ; CHECK: @switch.table.bar = private unnamed_addr constant [4 x i32] [i32 55, i32 123, i32 0, i32 -1]
 ; CHECK-LABEL: foo
 ; CHECK-NOT: @switch.table.foo = private unnamed_addr constant [4 x i32] [i32 55, i32 123, i32 0, i32 -1]
 
 define i32 @foo(i32 %c) "no-jump-tables"="true" {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 42, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 43, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 44, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    i32 45, label [[SW_BB3:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb3:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 15, [[SW_DEFAULT]] ], [ -1, [[SW_BB3]] ], [ 0, [[SW_BB2]] ], [ 123, [[SW_BB1]] ], [ 55, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 42, label %return
-    i32 43, label %sw.bb1
-    i32 44, label %sw.bb2
-    i32 45, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

   ret i32 %retval.0
 }
 
 
 define i32 @bar(i32 %c) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.bar, i32 0, i32 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 15
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 42, label %return
-    i32 43, label %sw.bb1
-    i32 44, label %sw.bb2
-    i32 45, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

test/Transforms/SimplifyCFG/X86/speculate-cttz-ctlz.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown -mattr=+bmi < %s | FileCheck %s --check-prefix=ALL --check-prefix=BMI
 ; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown -mattr=+lzcnt < %s | FileCheck %s --check-prefix=ALL --check-prefix=LZCNT
 ; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefix=ALL --check-prefix=GENERIC
 
 
 define i64 @test1(i64 %A) {
-; ALL-LABEL: @test1(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
-; ALL: ret
+; BMI-LABEL: @test1(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[A]], i1 true)
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; BMI-NEXT:    ret i64 [[COND]]
+;
+; LZCNT-LABEL: @test1(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[A]], i1 true)
+; LZCNT-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; LZCNT-NEXT:    ret i64 [[SPEC_SELECT]]
+;
+; GENERIC-LABEL: @test1(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; GENERIC-NEXT:    ret i64 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
   ret i64 %cond
 }
 
 define i32 @test2(i32 %A) {
-; ALL-LABEL: @test2(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
-; ALL: ret
+; BMI-LABEL: @test2(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[A]], i1 true)
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; BMI-NEXT:    ret i32 [[COND]]
+;
+; LZCNT-LABEL: @test2(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[A]], i1 true)
+; LZCNT-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; LZCNT-NEXT:    ret i32 [[SPEC_SELECT]]
+;
+; GENERIC-LABEL: @test2(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; GENERIC-NEXT:    ret i32 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   ret i32 %cond
 }
 
 
 define signext i16 @test3(i16 signext %A) {
-; ALL-LABEL: @test3(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
-; ALL: ret
+; BMI-LABEL: @test3(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[A]], i1 true)
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; BMI-NEXT:    ret i16 [[COND]]
+;
+; LZCNT-LABEL: @test3(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[A]], i1 true)
+; LZCNT-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; LZCNT-NEXT:    ret i16 [[SPEC_SELECT]]
+;
+; GENERIC-LABEL: @test3(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i16 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   ret i16 %cond
 }
 
 
 define i64 @test1b(i64 %A) {
-; ALL-LABEL: @test1b(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
-; ALL: ret
+; BMI-LABEL: @test1b(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[A]], i1 true)
+; BMI-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; BMI-NEXT:    ret i64 [[SPEC_SELECT]]
+;
+; LZCNT-LABEL: @test1b(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[A]], i1 true)
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; LZCNT-NEXT:    ret i64 [[COND]]
+;
+; GENERIC-LABEL: @test1b(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
+; GENERIC-NEXT:    ret i64 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   ret i64 %cond
 }
 
 
 define i32 @test2b(i32 %A) {
-; ALL-LABEL: @test2b(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
-; ALL: ret
+; BMI-LABEL: @test2b(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[A]], i1 true)
+; BMI-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; BMI-NEXT:    ret i32 [[SPEC_SELECT]]
+;
+; LZCNT-LABEL: @test2b(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[A]], i1 true)
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; LZCNT-NEXT:    ret i32 [[COND]]
+;
+; GENERIC-LABEL: @test2b(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
+; GENERIC-NEXT:    ret i32 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   ret i32 %cond
 }
 
 
 define signext i16 @test3b(i16 signext %A) {
-; ALL-LABEL: @test3b(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
-; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
-; ALL: ret
+; BMI-LABEL: @test3b(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[A]], i1 true)
+; BMI-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; BMI-NEXT:    ret i16 [[SPEC_SELECT]]
+;
+; LZCNT-LABEL: @test3b(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[A]], i1 true)
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; LZCNT-NEXT:    ret i16 [[COND]]
+;
+; GENERIC-LABEL: @test3b(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[A]], i1 true)
+; GENERIC-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i16 %A, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

 ; The following tests verify that calls to cttz/ctlz are speculated even if
 ; basic block %cond.true has an extra zero extend/truncate which is "free"
 ; for the target.
 
 define i64 @test1e(i32 %x) {
-; ALL-LABEL: @test1e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
-; BMI-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
-; LZCNT-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test1e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; BMI-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 32, i64 [[PHITMP2]]
+; BMI-NEXT:    ret i64 [[COND]]
+;
+; LZCNT-LABEL: @test1e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; LZCNT-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; LZCNT:       cond.true:
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; LZCNT-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; LZCNT-NEXT:    br label [[COND_END]]
+; LZCNT:       cond.end:
+; LZCNT-NEXT:    [[COND:%.*]] = phi i64 [ [[PHITMP2]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; LZCNT-NEXT:    ret i64 [[COND]]
+;
+; GENERIC-LABEL: @test1e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; GENERIC-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i64 [ [[PHITMP2]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i64 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
   ret i64 %cond
 }
 
 define i32 @test2e(i64 %x) {
-; ALL-LABEL: @test2e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
-; BMI-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
-; LZCNT-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test2e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]]
+; BMI-NEXT:    ret i32 [[COND]]
+;
+; LZCNT-LABEL: @test2e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; LZCNT-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; LZCNT:       cond.true:
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; LZCNT-NEXT:    br label [[COND_END]]
+; LZCNT:       cond.end:
+; LZCNT-NEXT:    [[COND:%.*]] = phi i32 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; LZCNT-NEXT:    ret i32 [[COND]]
+;
+; GENERIC-LABEL: @test2e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i32 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i32 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
   ret i32 %cond
 }
 
 define i64 @test3e(i32 %x) {
-; ALL-LABEL: @test3e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
-; LZCNT-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
-; BMI-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test3e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; BMI-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; BMI:       cond.true:
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; BMI-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; BMI-NEXT:    br label [[COND_END]]
+; BMI:       cond.end:
+; BMI-NEXT:    [[COND:%.*]] = phi i64 [ [[PHITMP2]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; BMI-NEXT:    ret i64 [[COND]]
+;
+; LZCNT-LABEL: @test3e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; LZCNT-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i64 32, i64 [[PHITMP2]]
+; LZCNT-NEXT:    ret i64 [[COND]]
+;
+; GENERIC-LABEL: @test3e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; GENERIC-NEXT:    [[PHITMP2:%.*]] = zext i32 [[TMP0]] to i64
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i64 [ [[PHITMP2]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i64 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
   ret i64 %cond
 }
 
 define i32 @test4e(i64 %x) {
-; ALL-LABEL: @test4e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
-; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
-; BMI-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test4e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; BMI-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; BMI:       cond.true:
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; BMI-NEXT:    br label [[COND_END]]
+; BMI:       cond.end:
+; BMI-NEXT:    [[COND:%.*]] = phi i32 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; BMI-NEXT:    ret i32 [[COND]]
+;
+; LZCNT-LABEL: @test4e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]]
+; LZCNT-NEXT:    ret i32 [[COND]]
+;
+; GENERIC-LABEL: @test4e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i32 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i32 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
   ret i32 %cond
 }
 
 define i16 @test5e(i64 %x) {
-; ALL-LABEL: @test5e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i16
-; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
-; BMI-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test5e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; BMI-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; BMI:       cond.true:
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; BMI-NEXT:    br label [[COND_END]]
+; BMI:       cond.end:
+; BMI-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; BMI-NEXT:    ret i16 [[COND]]
+;
+; LZCNT-LABEL: @test5e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 64, i16 [[CAST]]
+; LZCNT-NEXT:    ret i16 [[COND]]
+;
+; GENERIC-LABEL: @test5e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
   ret i16 %cond
 }
 
 define i16 @test6e(i32 %x) {
-; ALL-LABEL: @test6e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
-; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTLZ]] to i16
-; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
-; BMI-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test6e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; BMI-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; BMI:       cond.true:
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; BMI-NEXT:    br label [[COND_END]]
+; BMI:       cond.end:
+; BMI-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; BMI-NEXT:    ret i16 [[COND]]
+;
+; LZCNT-LABEL: @test6e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; LZCNT-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 32, i16 [[CAST]]
+; LZCNT-NEXT:    ret i16 [[COND]]
+;
+; GENERIC-LABEL: @test6e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i16 [ %cast, %cond.true ], [ 32, %entry ]
   ret i16 %cond
 }
 
 define i16 @test7e(i64 %x) {
-; ALL-LABEL: @test7e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i16
-; BMI-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
-; LZCNT-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test7e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 64, i16 [[CAST]]
+; BMI-NEXT:    ret i16 [[COND]]
+;
+; LZCNT-LABEL: @test7e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; LZCNT-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; LZCNT:       cond.true:
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; LZCNT-NEXT:    br label [[COND_END]]
+; LZCNT:       cond.end:
+; LZCNT-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; LZCNT-NEXT:    ret i16 [[COND]]
+;
+; GENERIC-LABEL: @test7e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 64, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i64 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

   %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
   ret i16 %cond
 }
 
 define i16 @test8e(i32 %x) {
-; ALL-LABEL: @test8e(
-; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
-; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTTZ]] to i16
-; BMI-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
-; LZCNT-NOT: select
-; GENERIC-NOT: select
-; ALL: ret
+; BMI-LABEL: @test8e(
+; BMI-NEXT:  entry:
+; BMI-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; BMI-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; BMI-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; BMI-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i16 32, i16 [[CAST]]
+; BMI-NEXT:    ret i16 [[COND]]
+;
+; LZCNT-LABEL: @test8e(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; LZCNT-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; LZCNT:       cond.true:
+; LZCNT-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; LZCNT-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; LZCNT-NEXT:    br label [[COND_END]]
+; LZCNT:       cond.end:
+; LZCNT-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; LZCNT-NEXT:    ret i16 [[COND]]
+;
+; GENERIC-LABEL: @test8e(
+; GENERIC-NEXT:  entry:
+; GENERIC-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0
+; GENERIC-NEXT:    br i1 [[TOBOOL]], label [[COND_END:%.*]], label [[COND_TRUE:%.*]]
+; GENERIC:       cond.true:
+; GENERIC-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true)
+; GENERIC-NEXT:    [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
+; GENERIC-NEXT:    br label [[COND_END]]
+; GENERIC:       cond.end:
+; GENERIC-NEXT:    [[COND:%.*]] = phi i16 [ [[CAST]], [[COND_TRUE]] ], [ 32, [[ENTRY:%.*]] ]
+; GENERIC-NEXT:    ret i16 [[COND]]
+;
 entry:
   %tobool = icmp eq i32 %x, 0
   br i1 %tobool, label %cond.end, label %cond.true
 
 cond.true:                                        ; preds = %entry

test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
 ; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
 
 ; rdar://17887153
 target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin12.0.0"
 
-; When we have a covered lookup table, make sure we don't delete PHINodes that
-; are cached in PHIs.
-; CHECK-LABEL: @test
-; CHECK: entry:
-; CHECK-NEXT: sub i3 %arg, -4
-; CHECK-NEXT: zext i3 %switch.tableidx to i4
-; CHECK-NEXT: getelementptr inbounds [8 x i64], [8 x i64]* @switch.table.test, i32 0, i4 %switch.tableidx.zext
-; CHECK-NEXT: load i64, i64* %switch.gep
-; CHECK-NEXT: add i64
-; CHECK-NEXT: ret i64
 define i64 @test(i3 %arg) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], -4
+; CHECK-NEXT:    [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]]
+; CHECK-NEXT:    [[V3:%.*]] = add i64 [[SWITCH_LOAD]], 0
+; CHECK-NEXT:    ret i64 [[V3]]
+;
 entry:
   switch i3 %arg, label %Default [
-    i3 -2, label %Label6
-    i3 1, label %Label1
-    i3 2, label %Label2
-    i3 3, label %Label3
-    i3 -4, label %Label4
-    i3 -3, label %Label5
   ]
 
 Default:
   %v1 = phi i64 [ 7, %Label6 ], [ 11, %Label5 ], [ 6, %Label4 ], [ 13, %Label3 ], [ 9, %Label2 ], [ 15, %Label1 ], [ 8, %entry ]
   %v2 = phi i64 [ 0, %Label6 ], [ 0, %Label5 ], [ 0, %Label4 ], [ 0, %Label3 ], [ 0, %Label2 ], [ 0, %Label1 ], [ 0, %entry ]

test/Transforms/SimplifyCFG/X86/switch-table-bug.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
 ; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
 
 ; rdar://17735071
 target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin12.0.0"
 
-; When tableindex can't fit into i2, we should extend the type to i3.
-; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si
-; CHECK: entry:
-; CHECK-NEXT: sub i2 %0, -2
-; CHECK-NEXT: zext i2 %switch.tableidx to i3
-; CHECK-NEXT: getelementptr inbounds [4 x i64], [4 x i64]* @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 %switch.tableidx.zext
-; CHECK-NEXT: load i64, i64* %switch.gep
-; CHECK-NEXT: ret i64 %switch.load
 define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) {
+; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2
+; CHECK-NEXT:    [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i64 [[SWITCH_LOAD]]
+;
 entry:
   switch i2 %0, label %1 [
-    i2 0, label %2
-    i2 1, label %3
-    i2 -2, label %4
-    i2 -1, label %5
   ]
 
 ; <label>:1                                       ; preds = %entry
   unreachable
 

test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -switch-to-lookup=true -keep-loops=false -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 ; RUN: opt < %s -passes='simplify-cfg<no-keep-loops;switch-to-lookup>' -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 

 ; It is dense enough to be replaced by table lookup.
 ; The result is directly by a ret from an otherwise empty bb,
 ; so we return early, directly from the lookup bb.
 
 define i32 @f(i32 %c) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i32 0, i32 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 15
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 42, label %return
-    i32 43, label %sw.bb1
-    i32 44, label %sw.bb2
-    i32 45, label %sw.bb3
-    i32 46, label %sw.bb4
-    i32 47, label %sw.bb5
-    i32 48, label %sw.bb6
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

 sw.default: br label %return
 return:
   %retval.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @f(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i32 %c, 42
-; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 7
-; CHECK-NEXT: br i1 %0, label %switch.lookup, label %return
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
-; CHECK-NEXT: ret i32 %switch.load
-; CHECK: return:
-; CHECK-NEXT: ret i32 15
 }
 
 ; Same thing, but with i8's
 
 define i8 @char(i32 %c) {
+; CHECK-LABEL: @char(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 9
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i8], [9 x i8]* @switch.table.char, i32 0, i32 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i8, i8* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i8 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i8 15
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 42, label %return
-    i32 43, label %sw.bb1
-    i32 44, label %sw.bb2
-    i32 45, label %sw.bb3
-    i32 46, label %sw.bb4
-    i32 47, label %sw.bb5
-    i32 48, label %sw.bb6
-    i32 49, label %sw.bb7
-    i32 50, label %sw.bb8
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

 sw.default: br label %return
 return:
   %retval.0 = phi i8 [ 15, %sw.default ], [ 84, %sw.bb8 ], [ 33, %sw.bb7 ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i8 %retval.0
 
-; CHECK-LABEL: @char(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i32 %c, 42
-; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 9
-; CHECK-NEXT: br i1 %0, label %switch.lookup, label %return
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [9 x i8], [9 x i8]* @switch.table.char, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load i8, i8* %switch.gep
-; CHECK-NEXT: ret i8 %switch.load
-; CHECK: return:
-; CHECK-NEXT: ret i8 15
 }
 
 ; A switch used to initialize two variables, an i8 and a float.
 
 declare void @dummy(i8 signext, float)
 define void @h(i32 %x) {
+; CHECK-LABEL: @h(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_EPILOG:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_SHIFTAMT:%.*]] = mul i32 [[X]], 8
+; CHECK-NEXT:    [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 89655594, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT:    [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x float], [4 x float]* @switch.table.h, i32 0, i32 [[X]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load float, float* [[SWITCH_GEP]]
+; CHECK-NEXT:    br label [[SW_EPILOG]]
+; CHECK:       sw.epilog:
+; CHECK-NEXT:    [[A_0:%.*]] = phi i8 [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 0x4023FAE140000000, [[ENTRY]] ]
+; CHECK-NEXT:    call void @dummy(i8 signext [[A_0]], float [[B_0]])
+; CHECK-NEXT:    ret void
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.epilog
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

   %a.0 = phi i8 [ 7, %sw.default ], [ 5, %sw.bb3 ], [ 88, %sw.bb2 ], [ 9, %sw.bb1 ], [ 42, %entry ]
   %b.0 = phi float [ 0x4023FAE140000000, %sw.default ], [ 0x4001AE1480000000, %sw.bb3 ], [ 0x4012449BA0000000, %sw.bb2 ], [ 0x3FF3BE76C0000000, %sw.bb1 ], [ 0x40091EB860000000, %entry ]
   call void @dummy(i8 signext %a.0, float %b.0)
   ret void
 
-; CHECK-LABEL: @h(
-; CHECK: entry:
-; CHECK-NEXT: %0 = icmp ult i32 %x, 4
-; CHECK-NEXT: br i1 %0, label %switch.lookup, label %sw.epilog
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.shiftamt = mul i32 %x, 8
-; CHECK-NEXT: %switch.downshift = lshr i32 89655594, %switch.shiftamt
-; CHECK-NEXT: %switch.masked = trunc i32 %switch.downshift to i8
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x float], [4 x float]* @switch.table.h, i32 0, i32 %x
-; CHECK-NEXT: %switch.load = load float, float* %switch.gep
-; CHECK-NEXT: br label %sw.epilog
-; CHECK: sw.epilog:
-; CHECK-NEXT: %a.0 = phi i8 [ %switch.masked, %switch.lookup ], [ 7, %entry ]
-; CHECK-NEXT: %b.0 = phi float [ %switch.load, %switch.lookup ], [ 0x4023FAE140000000, %entry ]
-; CHECK-NEXT: call void @dummy(i8 signext %a.0, float %b.0)
-; CHECK-NEXT: ret void
 }
 
 
 ; Switch used to return a string.
 

 @.str2 = private unnamed_addr constant [4 x i8] c"baz\00", align 1
 @.str3 = private unnamed_addr constant [4 x i8] c"qux\00", align 1
 @.str4 = private unnamed_addr constant [6 x i8] c"error\00", align 1
 
 define i8* @foostring(i32 %x)  {
+; CHECK-LABEL: @foostring(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* @switch.table.foostring, i32 0, i32 [[X]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i8*, i8** [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i8* [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0)
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: br label %return
 
 return:
   %retval.0 = phi i8* [ getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), %sw.default ],
-                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
-                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
-                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
-                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), %entry ]
   ret i8* %retval.0
 
-; CHECK-LABEL: @foostring(
-; CHECK: entry:
-; CHECK-NEXT: %0 = icmp ult i32 %x, 4
-; CHECK-NEXT: br i1 %0, label %switch.lookup, label %return
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i8*], [4 x i8*]* @switch.table.foostring, i32 0, i32 %x
-; CHECK-NEXT: %switch.load = load i8*, i8** %switch.gep
-; CHECK-NEXT: ret i8* %switch.load
 }
 
 ; Switch used to initialize two values. The first value is returned, the second
 ; value is not used. This used to make the transformation generate illegal code.
 
 define i32 @earlyreturncrash(i32 %x)  {
+; CHECK-LABEL: @earlyreturncrash(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_EPILOG:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.earlyreturncrash, i32 0, i32 [[X]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       sw.epilog:
+; CHECK-NEXT:    ret i32 7
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.epilog
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

 sw.epilog:
   %a.0 = phi i32 [ 7, %sw.default ], [ 5, %sw.bb3 ], [ 88, %sw.bb2 ], [ 9, %sw.bb1 ], [ 42, %entry ]
   %b.0 = phi i32 [ 10, %sw.default ], [ 5, %sw.bb3 ], [ 1, %sw.bb2 ], [ 4, %sw.bb1 ], [ 3, %entry ]
   ret i32 %a.0
 
-; CHECK-LABEL: @earlyreturncrash(
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.earlyreturncrash, i32 0, i32 %x
-; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
-; CHECK-NEXT: ret i32 %switch.load
-; CHECK: sw.epilog:
-; CHECK-NEXT: ret i32 7
 }
 
 
 ; Example 7 from http://blog.regehr.org/archives/320
 ; It is not dense enough for a regular table, but the results
 ; can be packed into a bitmap.
 
 define i32 @crud(i8 zeroext %c)  {
+; CHECK-LABEL: @crud(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C]], 34
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 59
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[LOR_END]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i59
+; CHECK-NEXT:    [[SWITCH_SHIFTAMT:%.*]] = mul i59 [[SWITCH_CAST]], 1
+; CHECK-NEXT:    [[SWITCH_DOWNSHIFT:%.*]] = lshr i59 -288230375765830623, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT:    [[SWITCH_MASKED:%.*]] = trunc i59 [[SWITCH_DOWNSHIFT]] to i1
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ false, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   %cmp = icmp ult i8 %c, 33
   br i1 %cmp, label %lor.end, label %switch.early.test
 
 switch.early.test:
   switch i8 %c, label %lor.rhs [
-    i8 92, label %lor.end
-    i8 62, label %lor.end
-    i8 60, label %lor.end
-    i8 59, label %lor.end
-    i8 58, label %lor.end
-    i8 46, label %lor.end
-    i8 44, label %lor.end
-    i8 34, label %lor.end
-    i8 39, label %switch.edge
   ]
 
 switch.edge: br label %lor.end
 lor.rhs: br label %lor.end
 
 lor.end:
   %0 = phi i1 [ true, %switch.early.test ],
-              [ false, %lor.rhs ],
-              [ true, %entry ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.early.test ],
-              [ true, %switch.edge ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK-LABEL: @crud(
-; CHECK: entry:
-; CHECK-NEXT: %cmp = icmp ult i8 %c, 33
-; CHECK-NEXT: br i1 %cmp, label %lor.end, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK-NEXT: %switch.tableidx = sub i8 %c, 34
-; CHECK-NEXT: %0 = icmp ult i8 %switch.tableidx, 59
-; CHECK-NEXT: br i1 %0, label %switch.lookup, label %lor.end
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.cast = zext i8 %switch.tableidx to i59
-; CHECK-NEXT: %switch.shiftamt = mul i59 %switch.cast, 1
-; CHECK-NEXT: %switch.downshift = lshr i59 -288230375765830623, %switch.shiftamt
-; CHECK-NEXT: %switch.masked = trunc i59 %switch.downshift to i1
-; CHECK-NEXT: br label %lor.end
-; CHECK: lor.end:
-; CHECK-NEXT: %1 = phi i1 [ true, %entry ], [ %switch.masked, %switch.lookup ], [ false, %switch.early.test ]
-; CHECK-NEXT: %lor.ext = zext i1 %1 to i32
-; CHECK-NEXT: ret i32 %lor.ext
 }
 
 ; PR13946
 define i32 @overflow(i32 %type) {
+; CHECK-LABEL: @overflow(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[TYPE:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 3, label [[SW_BB3:%.*]]
+; CHECK-NEXT:    i32 -2147483645, label [[SW_BB3]]
+; CHECK-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       sw.bb3:
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[DIRENT_TYPE_0:%.*]] = phi i32 [ 6, [[SW_BB3]] ], [ 5, [[SW_BB2]] ], [ 0, [[SW_BB1]] ], [ 3, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[DIRENT_TYPE_0]]
+;
 entry:
   switch i32 %type, label %sw.default [
-    i32 -2147483648, label %sw.bb
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 -2147483645, label %sw.bb3
-    i32 3, label %sw.bb3
   ]
 
 sw.bb: br label %if.end
 sw.bb1: br label %if.end
 sw.bb2: br label %if.end

 if.else: br label %if.end
 
 if.end:
   %dirent_type.0 = phi i32 [ 3, %sw.default ], [ 6, %sw.bb3 ], [ 5, %sw.bb2 ], [ 0, %sw.bb1 ], [ 3, %sw.bb ], [ 0, %if.else ]
   ret i32 %dirent_type.0
-; CHECK-LABEL: define i32 @overflow(
-; CHECK: switch
-; CHECK: phi
 }
 
 ; PR13985
 define i1 @undef(i32 %tmp) {
+; CHECK-LABEL: @undef(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[TMP:%.*]], 9
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[BB3:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_CAST:%.*]] = trunc i32 [[TMP]] to i9
+; CHECK-NEXT:    [[SWITCH_SHIFTAMT:%.*]] = mul i9 [[SWITCH_CAST]], 1
+; CHECK-NEXT:    [[SWITCH_DOWNSHIFT:%.*]] = lshr i9 3, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT:    [[SWITCH_MASKED:%.*]] = trunc i9 [[SWITCH_DOWNSHIFT]] to i1
+; CHECK-NEXT:    ret i1 [[SWITCH_MASKED]]
+; CHECK:       bb3:
+; CHECK-NEXT:    ret i1 undef
+;
 bb:
   switch i32 %tmp, label %bb3 [
-    i32 0, label %bb1
-    i32 1, label %bb1
-    i32 7, label %bb2
-    i32 8, label %bb2
   ]
 
 bb1: br label %bb3
 bb2: br label %bb3
 
 bb3:
   %tmp4 = phi i1 [ undef, %bb ], [ false, %bb2 ], [ true, %bb1 ]
   ret i1 %tmp4
-; CHECK-LABEL: define i1 @undef(
-; CHECK: %switch.cast = trunc i32 %tmp to i9
-; CHECK: %switch.downshift = lshr i9 3, %switch.shiftamt
 }
 
 ; Also handle large switches that would be rejected by
 ; isValueEqualityComparison()
-; CHECK: large
-; CHECK-NOT: switch i32
+
 define i32 @large(i32 %x) {
+; CHECK-LABEL: @large(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[X]], -10
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[MUL]], i32 [[X]]
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[SPEC_SELECT]], 1
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 199
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [199 x i32], [199 x i32]* @switch.table.large, i32 0, i32 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 0
+;
 entry:
   %cmp = icmp slt i32 %x, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:

   br label %if.end
 
 if.end:
   %x.addr.0 = phi i32 [ %mul, %if.then ], [ %x, %entry ]
   switch i32 %x.addr.0, label %return [
-    i32 199, label %sw.bb203
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
-    i32 4, label %sw.bb4
-    i32 5, label %sw.bb5
-    i32 6, label %sw.bb6
-    i32 7, label %sw.bb7
-    i32 8, label %sw.bb8
-    i32 9, label %sw.bb9
-    i32 10, label %sw.bb10
-    i32 11, label %sw.bb11
-    i32 12, label %sw.bb12
-    i32 13, label %sw.bb13
-    i32 14, label %sw.bb14
-    i32 15, label %sw.bb15
-    i32 16, label %sw.bb16
-    i32 17, label %sw.bb17
-    i32 18, label %sw.bb18
-    i32 19, label %sw.bb19
-    i32 20, label %sw.bb20
-    i32 21, label %sw.bb21
-    i32 22, label %sw.bb22
-    i32 23, label %sw.bb23
-    i32 24, label %sw.bb24
-    i32 25, label %sw.bb25
-    i32 26, label %sw.bb26
-    i32 27, label %sw.bb27
-    i32 28, label %sw.bb28
-    i32 29, label %sw.bb29
-    i32 30, label %sw.bb30
-    i32 31, label %sw.bb31
-    i32 32, label %sw.bb32
-    i32 33, label %sw.bb33
-    i32 34, label %sw.bb34
-    i32 35, label %sw.bb35
-    i32 36, label %sw.bb37
-    i32 37, label %sw.bb38
-    i32 38, label %sw.bb39
-    i32 39, label %sw.bb40
-    i32 40, label %sw.bb41
-    i32 41, label %sw.bb42
-    i32 42, label %sw.bb43
-    i32 43, label %sw.bb44
-    i32 44, label %sw.bb45
-    i32 45, label %sw.bb47
-    i32 46, label %sw.bb48
-    i32 47, label %sw.bb49
-    i32 48, label %sw.bb50
-    i32 49, label %sw.bb51
-    i32 50, label %sw.bb52
-    i32 51, label %sw.bb53
-    i32 52, label %sw.bb54
-    i32 53, label %sw.bb55
-    i32 54, label %sw.bb56
-    i32 55, label %sw.bb58
-    i32 56, label %sw.bb59
-    i32 57, label %sw.bb60
-    i32 58, label %sw.bb61
-    i32 59, label %sw.bb62
-    i32 60, label %sw.bb63
-    i32 61, label %sw.bb64
-    i32 62, label %sw.bb65
-    i32 63, label %sw.bb66
-    i32 64, label %sw.bb67
-    i32 65, label %sw.bb68
-    i32 66, label %sw.bb69
-    i32 67, label %sw.bb70
-    i32 68, label %sw.bb71
-    i32 69, label %sw.bb72
-    i32 70, label %sw.bb73
-    i32 71, label %sw.bb74
-    i32 72, label %sw.bb76
-    i32 73, label %sw.bb77
-    i32 74, label %sw.bb78
-    i32 75, label %sw.bb79
-    i32 76, label %sw.bb80
-    i32 77, label %sw.bb81
-    i32 78, label %sw.bb82
-    i32 79, label %sw.bb83
-    i32 80, label %sw.bb84
-    i32 81, label %sw.bb85
-    i32 82, label %sw.bb86
-    i32 83, label %sw.bb87
-    i32 84, label %sw.bb88
-    i32 85, label %sw.bb89
-    i32 86, label %sw.bb90
-    i32 87, label %sw.bb91
-    i32 88, label %sw.bb92
-    i32 89, label %sw.bb93
-    i32 90, label %sw.bb94
-    i32 91, label %sw.bb95
-    i32 92, label %sw.bb96
-    i32 93, label %sw.bb97
-    i32 94, label %sw.bb98
-    i32 95, label %sw.bb99
-    i32 96, label %sw.bb100
-    i32 97, label %sw.bb101
-    i32 98, label %sw.bb102
-    i32 99, label %sw.bb103
-    i32 100, label %sw.bb104
-    i32 101, label %sw.bb105
-    i32 102, label %sw.bb106
-    i32 103, label %sw.bb107
-    i32 104, label %sw.bb108
-    i32 105, label %sw.bb109
-    i32 106, label %sw.bb110
-    i32 107, label %sw.bb111
-    i32 108, label %sw.bb112
-    i32 109, label %sw.bb113
-    i32 110, label %sw.bb114
-    i32 111, label %sw.bb115
-    i32 112, label %sw.bb116
-    i32 113, label %sw.bb117
-    i32 114, label %sw.bb118
-    i32 115, label %sw.bb119
-    i32 116, label %sw.bb120
-    i32 117, label %sw.bb121
-    i32 118, label %sw.bb122
-    i32 119, label %sw.bb123
-    i32 120, label %sw.bb124
-    i32 121, label %sw.bb125
-    i32 122, label %sw.bb126
-    i32 123, label %sw.bb127
-    i32 124, label %sw.bb128
-    i32 125, label %sw.bb129
-    i32 126, label %sw.bb130
-    i32 127, label %sw.bb131
-    i32 128, label %sw.bb132
-    i32 129, label %sw.bb133
-    i32 130, label %sw.bb134
-    i32 131, label %sw.bb135
-    i32 132, label %sw.bb136
-    i32 133, label %sw.bb137
-    i32 134, label %sw.bb138
-    i32 135, label %sw.bb139
-    i32 136, label %sw.bb140
-    i32 137, label %sw.bb141
-    i32 138, label %sw.bb142
-    i32 139, label %sw.bb143
-    i32 140, label %sw.bb144
-    i32 141, label %sw.bb145
-    i32 142, label %sw.bb146
-    i32 143, label %sw.bb147
-    i32 144, label %sw.bb148
-    i32 145, label %sw.bb149
-    i32 146, label %sw.bb150
-    i32 147, label %sw.bb151
-    i32 148, label %sw.bb152
-    i32 149, label %sw.bb153
-    i32 150, label %sw.bb154
-    i32 151, label %sw.bb155
-    i32 152, label %sw.bb156
-    i32 153, label %sw.bb157
-    i32 154, label %sw.bb158
-    i32 155, label %sw.bb159
-    i32 156, label %sw.bb160
-    i32 157, label %sw.bb161
-    i32 158, label %sw.bb162
-    i32 159, label %sw.bb163
-    i32 160, label %sw.bb164
-    i32 161, label %sw.bb165
-    i32 162, label %sw.bb166
-    i32 163, label %sw.bb167
-    i32 164, label %sw.bb168
-    i32 165, label %sw.bb169
-    i32 166, label %sw.bb170
-    i32 167, label %sw.bb171
-    i32 168, label %sw.bb172
-    i32 169, label %sw.bb173
-    i32 170, label %sw.bb174
-    i32 171, label %sw.bb175
-    i32 172, label %sw.bb176
-    i32 173, label %sw.bb177
-    i32 174, label %sw.bb178
-    i32 175, label %sw.bb179
-    i32 176, label %sw.bb180
-    i32 177, label %sw.bb181
-    i32 178, label %sw.bb182
-    i32 179, label %sw.bb183
-    i32 180, label %sw.bb184
-    i32 181, label %sw.bb185
-    i32 182, label %sw.bb186
-    i32 183, label %sw.bb187
-    i32 184, label %sw.bb188
-    i32 185, label %sw.bb189
-    i32 186, label %sw.bb190
-    i32 187, label %sw.bb191
-    i32 188, label %sw.bb192
-    i32 189, label %sw.bb193
-    i32 190, label %sw.bb194
-    i32 191, label %sw.bb195
-    i32 192, label %sw.bb196
-    i32 193, label %sw.bb197
-    i32 194, label %sw.bb198
-    i32 195, label %sw.bb199
-    i32 196, label %sw.bb200
-    i32 197, label %sw.bb201
-    i32 198, label %sw.bb202
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

   %retval.0 = phi i32 [ 39204, %sw.bb202 ], [ 38809, %sw.bb201 ], [ 38416, %sw.bb200 ], [ 38025, %sw.bb199 ], [ 37636, %sw.bb198 ], [ 37249, %sw.bb197 ], [ 36864, %sw.bb196 ], [ 36481, %sw.bb195 ], [ 36100, %sw.bb194 ], [ 35721, %sw.bb193 ], [ 35344, %sw.bb192 ], [ 34969, %sw.bb191 ], [ 34596, %sw.bb190 ], [ 34225, %sw.bb189 ], [ 33856, %sw.bb188 ], [ 33489, %sw.bb187 ], [ 33124, %sw.bb186 ], [ 32761, %sw.bb185 ], [ 32400, %sw.bb184 ], [ 32041, %sw.bb183 ], [ 31684, %sw.bb182 ], [ 31329, %sw.bb181 ], [ 30976, %sw.bb180 ], [ 30625, %sw.bb179 ], [ 30276, %sw.bb178 ], [ 29929, %sw.bb177 ], [ 29584, %sw.bb176 ], [ 29241, %sw.bb175 ], [ 28900, %sw.bb174 ], [ 28561, %sw.bb173 ], [ 28224, %sw.bb172 ], [ 27889, %sw.bb171 ], [ 27556, %sw.bb170 ], [ 27225, %sw.bb169 ], [ 26896, %sw.bb168 ], [ 26569, %sw.bb167 ], [ 26244, %sw.bb166 ], [ 25921, %sw.bb165 ], [ 25600, %sw.bb164 ], [ 25281, %sw.bb163 ], [ 24964, %sw.bb162 ], [ 24649, %sw.bb161 ], [ 24336, %sw.bb160 ], [ 24025, %sw.bb159 ], [ 23716, %sw.bb158 ], [ 23409, %sw.bb157 ], [ 23104, %sw.bb156 ], [ 22801, %sw.bb155 ], [ 22500, %sw.bb154 ], [ 22201, %sw.bb153 ], [ 21904, %sw.bb152 ], [ 21609, %sw.bb151 ], [ 21316, %sw.bb150 ], [ 21025, %sw.bb149 ], [ 20736, %sw.bb148 ], [ 20449, %sw.bb147 ], [ 20164, %sw.bb146 ], [ 19881, %sw.bb145 ], [ 19600, %sw.bb144 ], [ 19321, %sw.bb143 ], [ 19044, %sw.bb142 ], [ 18769, %sw.bb141 ], [ 18496, %sw.bb140 ], [ 18225, %sw.bb139 ], [ 17956, %sw.bb138 ], [ 17689, %sw.bb137 ], [ 17424, %sw.bb136 ], [ 17161, %sw.bb135 ], [ 16900, %sw.bb134 ], [ 16641, %sw.bb133 ], [ 16384, %sw.bb132 ], [ 16129, %sw.bb131 ], [ 15876, %sw.bb130 ], [ 15625, %sw.bb129 ], [ 15376, %sw.bb128 ], [ 15129, %sw.bb127 ], [ 14884, %sw.bb126 ], [ 14641, %sw.bb125 ], [ 14400, %sw.bb124 ], [ 14161, %sw.bb123 ], [ 13924, %sw.bb122 ], [ 13689, %sw.bb121 ], [ 13456, %sw.bb120 ], [ 13225, %sw.bb119 ], [ 12996, %sw.bb118 ], [ 12769, %sw.bb117 ], [ 12544, %sw.bb116 ], [ 12321, %sw.bb115 ], [ 12100, %sw.bb114 ], [ 11881, %sw.bb113 ], [ 11664, %sw.bb112 ], [ 11449, %sw.bb111 ], [ 11236, %sw.bb110 ], [ 11025, %sw.bb109 ], [ 10816, %sw.bb108 ], [ 10609, %sw.bb107 ], [ 10404, %sw.bb106 ], [ 10201, %sw.bb105 ], [ 10000, %sw.bb104 ], [ 9801, %sw.bb103 ], [ 9604, %sw.bb102 ], [ 9409, %sw.bb101 ], [ 9216, %sw.bb100 ], [ 9025, %sw.bb99 ], [ 8836, %sw.bb98 ], [ 8649, %sw.bb97 ], [ 8464, %sw.bb96 ], [ 8281, %sw.bb95 ], [ 8100, %sw.bb94 ], [ 7921, %sw.bb93 ], [ 7744, %sw.bb92 ], [ 7569, %sw.bb91 ], [ 7396, %sw.bb90 ], [ 7225, %sw.bb89 ], [ 7056, %sw.bb88 ], [ 6889, %sw.bb87 ], [ 6724, %sw.bb86 ], [ 6561, %sw.bb85 ], [ 6400, %sw.bb84 ], [ 6241, %sw.bb83 ], [ 6084, %sw.bb82 ], [ 5929, %sw.bb81 ], [ 5776, %sw.bb80 ], [ 5625, %sw.bb79 ], [ 5476, %sw.bb78 ], [ 5329, %sw.bb77 ], [ 5184, %sw.bb76 ], [ 5112, %sw.bb74 ], [ 4900, %sw.bb73 ], [ 4761, %sw.bb72 ], [ 4624, %sw.bb71 ], [ 4489, %sw.bb70 ], [ 4356, %sw.bb69 ], [ 4225, %sw.bb68 ], [ 4096, %sw.bb67 ], [ 3969, %sw.bb66 ], [ 3844, %sw.bb65 ], [ 3721, %sw.bb64 ], [ 3600, %sw.bb63 ], [ 3481, %sw.bb62 ], [ 3364, %sw.bb61 ], [ 3249, %sw.bb60 ], [ 3136, %sw.bb59 ], [ 3025, %sw.bb58 ], [ 2970, %sw.bb56 ], [ 2809, %sw.bb55 ], [ 2704, %sw.bb54 ], [ 2601, %sw.bb53 ], [ 2500, %sw.bb52 ], [ 2401, %sw.bb51 ], [ 2304, %sw.bb50 ], [ 2209, %sw.bb49 ], [ 2116, %sw.bb48 ], [ 2025, %sw.bb47 ], [ 1980, %sw.bb45 ], [ 1849, %sw.bb44 ], [ 1764, %sw.bb43 ], [ 1681, %sw.bb42 ], [ 1600, %sw.bb41 ], [ 1521, %sw.bb40 ], [ 1444, %sw.bb39 ], [ 1369, %sw.bb38 ], [ 1296, %sw.bb37 ], [ 1260, %sw.bb35 ], [ 1156, %sw.bb34 ], [ 1089, %sw.bb33 ], [ 1024, %sw.bb32 ], [ 961, %sw.bb31 ], [ 900, %sw.bb30 ], [ 841, %sw.bb29 ], [ 784, %sw.bb28 ], [ 729, %sw.bb27 ], [ 676, %sw.bb26 ], [ 625, %sw.bb25 ], [ 576, %sw.bb24 ], [ 529, %sw.bb23 ], [ 484, %sw.bb22 ], [ 441, %sw.bb21 ], [ 400, %sw.bb20 ], [ 361, %sw.bb19 ], [ 342, %sw.bb18 ], [ 289, %sw.bb17 ], [ 256, %sw.bb16 ], [ 225, %sw.bb15 ], [ 196, %sw.bb14 ], [ 169, %sw.bb13 ], [ 144, %sw.bb12 ], [ 121, %sw.bb11 ], [ 100, %sw.bb10 ], [ 81, %sw.bb9 ], [ 64, %sw.bb8 ], [ 49, %sw.bb7 ], [ 36, %sw.bb6 ], [ 25, %sw.bb5 ], [ 16, %sw.bb4 ], [ 9, %sw.bb3 ], [ 4, %sw.bb2 ], [ 1, %sw.bb1 ], [ 39601, %sw.bb203 ], [ 0, %if.end ]
   ret i32 %retval.0
 }
 
 define i32 @cprop(i32 %x, i32 %y) {
+; CHECK-LABEL: @cprop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.cprop, i32 0, i32 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 123
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 1, label %return
-    i32 2, label %sw.bb1
-    i32 3, label %sw.bb2
-    i32 4, label %sw.bb2
-    i32 5, label %sw.bb2
-    i32 6, label %sw.bb3
-    i32 7, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 
 sw.bb2:

 
 return:
   %retval.0 = phi i32 [ 123, %sw.default ], [ %select, %sw.bb3 ], [ %sub, %sw.bb2 ], [ 42, %sw.bb1 ], [ 5, %entry ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @cprop(
-; CHECK: switch.lookup:
-; CHECK: %switch.gep = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.cprop, i32 0, i32 %switch.tableidx
 }
 
 define i32 @unreachable_case(i32 %x)  {
+; CHECK-LABEL: @unreachable_case(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 9
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.unreachable_case, i32 0, i32 [[X]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 2
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb
-    i32 2, label %sw.bb
-    i32 3, label %sw.bb1
-    i32 4, label %sw.bb2
-    i32 5, label %sw.bb3
-    i32 6, label %sw.bb3
-    i32 7, label %sw.bb3
-    i32 8, label %sw.bb3
   ]
 
 sw.bb: br label %return
 sw.bb1: unreachable
 sw.bb2: br label %return

 
 return:
   %retval.0 = phi i32 [ 1, %sw.bb3 ], [ -1, %sw.bb2 ], [ 0, %sw.bb ], [ 2, %sw.default ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @unreachable_case(
-; CHECK: switch.lookup:
-; CHECK: getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.unreachable_case, i32 0, i32 %x
 }
 
 define i32 @unreachable_default(i32 %x)  {
+; CHECK-LABEL: @unreachable_default(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.unreachable_default, i32 0, i32 [[X:%.*]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+;
 entry:
   switch i32 %x, label %default [
-    i32 0, label %bb0
-    i32 1, label %bb1
-    i32 2, label %bb2
-    i32 3, label %bb3
   ]
 
 bb0: br label %return
 bb1: br label %return
 bb2: br label %return

 
 return:
   %retval = phi i32 [ 42, %bb0 ], [ 52, %bb1 ], [ 1, %bb2 ], [ 2, %bb3 ]
   ret i32 %retval
 
-; CHECK-LABEL: @unreachable_default(
-; CHECK: entry:
-; CHECK-NOT: icmp
-; CHECK-NOT: br 1i
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.unreachable_default, i32 0, i32 %x
-; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
-; CHECK-NEXT: ret i32 %switch.load
 }
 
 ; Don't create a table with illegal type
 define i96 @illegaltype(i32 %c) {
+; CHECK-LABEL: @illegaltype(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 42, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 43, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 44, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    i32 45, label [[SW_BB3:%.*]]
+; CHECK-NEXT:    i32 46, label [[SW_BB4:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb3:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb4:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i96 [ 15, [[SW_DEFAULT]] ], [ 27, [[SW_BB4]] ], [ -1, [[SW_BB3]] ], [ 0, [[SW_BB2]] ], [ 123, [[SW_BB1]] ], [ 55, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i96 [[RETVAL_0]]
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 42, label %return
-    i32 43, label %sw.bb1
-    i32 44, label %sw.bb2
-    i32 45, label %sw.bb3
-    i32 46, label %sw.bb4
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return

 sw.default: br label %return
 return:
   %retval.0 = phi i96 [ 15, %sw.default ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i96 %retval.0
 
-; CHECK-LABEL: @illegaltype(
-; CHECK-NOT: @switch.table
-; CHECK: switch i32 %c
 }
 
 ; If we can build a lookup table without any holes, we don't need a default result.
 declare void @exit(i32)
 define i32 @nodefaultnoholes(i32 %c) {
+; CHECK-LABEL: @nodefaultnoholes(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_DEFAULT:%.*]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    call void @exit(i32 1)
+; CHECK-NEXT:    unreachable
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.nodefaultnoholes, i32 0, i32 [[C]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: call void @exit(i32 1)
-            unreachable
 return:
   %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i32 %x
 
-; CHECK-LABEL: @nodefaultnoholes(
-; CHECK: @switch.table
-; CHECK-NOT: switch i32
 }
 
 ; This lookup table will have holes, so we need to test for the holes.
 define i32 @nodefaultwithholes(i32 %c) {
+; CHECK-LABEL: @nodefaultwithholes(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 6
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_HOLE_CHECK:%.*]], label [[SW_DEFAULT:%.*]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    call void @exit(i32 1)
+; CHECK-NEXT:    unreachable
+; CHECK:       switch.hole_check:
+; CHECK-NEXT:    [[SWITCH_MASKINDEX:%.*]] = trunc i32 [[C]] to i8
+; CHECK-NEXT:    [[SWITCH_SHIFTED:%.*]] = lshr i8 47, [[SWITCH_MASKINDEX]]
+; CHECK-NEXT:    [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1
+; CHECK-NEXT:    br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[SW_DEFAULT]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.nodefaultwithholes, i32 0, i32 [[C]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
-    i32 5, label %sw.bb3
   ]
 
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: call void @exit(i32 1)
-            unreachable
 return:
   %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i32 %x
 
-; CHECK-LABEL: @nodefaultwithholes(
-; CHECK: entry:
-; CHECK: br i1 %{{.*}}, label %switch.hole_check, label %sw.default
-; CHECK: switch.hole_check:
-; CHECK-NEXT: %switch.maskindex = trunc i32 %c to i8
-; CHECK-NEXT: %switch.shifted = lshr i8 47, %switch.maskindex
 ; The mask is binary 101111.
-; CHECK-NEXT: %switch.lobit = trunc i8 %switch.shifted to i1
-; CHECK-NEXT: br i1 %switch.lobit, label %switch.lookup, label %sw.default
-; CHECK-NOT: switch i32
 }
 
 ; We don't build lookup tables with holes for switches with less than four cases.
 define i32 @threecasesholes(i32 %c) {
+; CHECK-LABEL: @threecasesholes(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 3, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[X:%.*]] = phi i32 [ [[C]], [[SW_DEFAULT]] ], [ 5, [[SW_BB2]] ], [ 7, [[SW_BB1]] ], [ 9, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[X]]
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 3, label %sw.bb2
   ]
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.default: br label %return
 return:
   %x = phi i32 [ %c, %sw.default ], [ 5, %sw.bb2 ], [ 7, %sw.bb1 ], [ 9, %entry ]
   ret i32 %x
-; CHECK-LABEL: @threecasesholes(
-; CHECK: switch i32
-; CHECK-NOT: @switch.table
 }
 
 ; We build lookup tables for switches with three or more cases.
 define i32 @threecases(i32 %c) {
 ; CHECK-LABEL: @threecases(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 %c, 3
-; CHECK-NEXT:    br i1 [[TMP0]], label %switch.lookup, label %return
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 3
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
 ; CHECK:       switch.lookup:
-; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* @switch.table.threecases, i32 0, i32 %c
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* @switch.table.threecases, i32 0, i32 [[C]]
 ; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
 ; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 3
 ;

 
 ; We don't build tables for switches with two cases.
 define i32 @twocases(i32 %c) {
 ; CHECK-LABEL: @twocases(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 %c, 1
-; CHECK-NEXT:    [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP:%.*]], i32 7, i32 3
-; CHECK-NEXT:    [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 %c, 0
+; CHECK-NEXT:    [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 [[C:%.*]], 1
+; CHECK-NEXT:    [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i32 7, i32 3
+; CHECK-NEXT:    [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 [[C]], 0
 ; CHECK-NEXT:    [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], i32 9, i32 [[SWITCH_SELECT]]
 ; CHECK-NEXT:    ret i32 [[SWITCH_SELECT2]]
 ;
 entry:
   switch i32 %c, label %sw.default [

 @tls_a = thread_local global i32 0
 @tls_b = thread_local global i32 0
 @tls_c = thread_local global i32 0
 @tls_d = thread_local global i32 0
 define i32* @tls(i32 %x) {
+; CHECK-LABEL: @tls(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32* [ @tls_d, [[SW_DEFAULT]] ], [ @tls_c, [[SW_BB2]] ], [ @tls_b, [[SW_BB1]] ], [ @tls_a, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32* [[RETVAL_0]]
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 sw.bb1:
   br label %return
 sw.bb2:
   br label %return
 sw.default:
   br label %return
 return:
   %retval.0 = phi i32* [ @tls_d, %sw.default ], [ @tls_c, %sw.bb2 ], [ @tls_b, %sw.bb1 ], [ @tls_a, %entry ]
   ret i32* %retval.0
-; CHECK-LABEL: @tls(
-; CHECK: switch i32
-; CHECK-NOT: @switch.table
 }
 
 ; Don't build tables for switches with dllimport variables.
 @dllimport_a = external dllimport global [3x i32]
 @dllimport_b = external dllimport global [3x i32]
 @dllimport_c = external dllimport global [3x i32]
 @dllimport_d = external dllimport global [3x i32]
 define i32* @dllimport(i32 %x) {
+; CHECK-LABEL: @dllimport(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 1, label [[SW_BB1:%.*]]
+; CHECK-NEXT:    i32 2, label [[SW_BB2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       sw.default:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_d, i32 0, i32 0), [[SW_DEFAULT]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_c, i32 0, i32 0), [[SW_BB2]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_b, i32 0, i32 0), [[SW_BB1]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_a, i32 0, i32 0), [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32* [[RETVAL_0]]
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %return
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
   ]
 sw.bb1:
   br label %return
 sw.bb2:
   br label %return
 sw.default:
   br label %return
 return:
   %retval.0 = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_d, i32 0, i32 0), %sw.default ],
-                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_c, i32 0, i32 0), %sw.bb2 ],
-                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_b, i32 0, i32 0), %sw.bb1 ],
-                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_a, i32 0, i32 0), %entry ]
   ret i32* %retval.0
-; CHECK-LABEL: @dllimport(
-; CHECK: switch i32
-; CHECK-NOT: @switch.table
 }
 
 ; We can use linear mapping.
 define i8 @linearmap1(i32 %c) {
+; CHECK-LABEL: @linearmap1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
+; CHECK-NEXT:    [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], -5
+; CHECK-NEXT:    [[SWITCH_OFFSET:%.*]] = add i8 [[SWITCH_IDX_MULT]], 18
+; CHECK-NEXT:    ret i8 [[SWITCH_OFFSET]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i8 3
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 10, label %return
-    i32 11, label %sw.bb1
-    i32 12, label %sw.bb2
-    i32 13, label %sw.bb3
   ]
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: br label %return
 return:
   %x = phi i8 [ 3, %sw.default ], [ 3, %sw.bb3 ], [ 8, %sw.bb2 ], [ 13, %sw.bb1 ], [ 18, %entry ]
   ret i8 %x
-; CHECK-LABEL: @linearmap1(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i32 %c, 10
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.idx.cast = trunc i32 %switch.tableidx to i8
-; CHECK-NEXT: %switch.idx.mult = mul i8 %switch.idx.cast, -5
-; CHECK-NEXT: %switch.offset = add i8 %switch.idx.mult, 18
-; CHECK-NEXT: ret i8 %switch.offset
 }
 
 ; Linear mapping in a different configuration.
 define i32 @linearmap2(i8 %c) {
+; CHECK-LABEL: @linearmap2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C:%.*]], -13
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_IDX_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i32
+; CHECK-NEXT:    [[SWITCH_OFFSET:%.*]] = add i32 [[SWITCH_IDX_CAST]], 18
+; CHECK-NEXT:    ret i32 [[SWITCH_OFFSET]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i32 3
+;
 entry:
   switch i8 %c, label %sw.default [
-    i8 -10, label %return
-    i8 -11, label %sw.bb1
-    i8 -12, label %sw.bb2
-    i8 -13, label %sw.bb3
   ]
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: br label %return
 return:
   %x = phi i32 [ 3, %sw.default ], [ 18, %sw.bb3 ], [ 19, %sw.bb2 ], [ 20, %sw.bb1 ], [ 21, %entry ]
   ret i32 %x
-; CHECK-LABEL: @linearmap2(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i8 %c, -13
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.idx.cast = zext i8 %switch.tableidx to i32
-; CHECK-NEXT: %switch.offset = add i32 %switch.idx.cast, 18
-; CHECK-NEXT: ret i32 %switch.offset
 }
 
 ; Linear mapping with overflows.
 define i8 @linearmap3(i32 %c) {
+; CHECK-LABEL: @linearmap3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
+; CHECK-NEXT:    [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], 100
+; CHECK-NEXT:    ret i8 [[SWITCH_IDX_MULT]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i8 3
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 10, label %return
-    i32 11, label %sw.bb1
-    i32 12, label %sw.bb2
-    i32 13, label %sw.bb3
   ]
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: br label %return
 return:
   %x = phi i8 [ 3, %sw.default ], [ 44, %sw.bb3 ], [ -56, %sw.bb2 ], [ 100, %sw.bb1 ], [ 0, %entry ]
   ret i8 %x
-; CHECK-LABEL: @linearmap3(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i32 %c, 10
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.idx.cast = trunc i32 %switch.tableidx to i8
-; CHECK-NEXT: %switch.idx.mult = mul i8 %switch.idx.cast, 100
-; CHECK-NEXT: ret i8 %switch.idx.mult
 }
 
 ; Linear mapping with with multiplier 1 and offset 0.
 define i8 @linearmap4(i32 %c) {
+; CHECK-LABEL: @linearmap4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], -2
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
+; CHECK-NEXT:    ret i8 [[SWITCH_IDX_CAST]]
+; CHECK:       return:
+; CHECK-NEXT:    ret i8 3
+;
 entry:
   switch i32 %c, label %sw.default [
-    i32 -2, label %return
-    i32 -1, label %sw.bb1
-    i32 0, label %sw.bb2
-    i32 1, label %sw.bb3
   ]
 sw.bb1: br label %return
 sw.bb2: br label %return
 sw.bb3: br label %return
 sw.default: br label %return
 return:
   %x = phi i8 [ 3, %sw.default ], [ 3, %sw.bb3 ], [ 2, %sw.bb2 ], [ 1, %sw.bb1 ], [ 0, %entry ]
   ret i8 %x
-; CHECK-LABEL: @linearmap4(
-; CHECK: entry:
-; CHECK-NEXT: %switch.tableidx = sub i32 %c, -2
-; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.idx.cast = trunc i32 %switch.tableidx to i8
-; CHECK-NEXT: ret i8 %switch.idx.cast
 }
 
 ; Reuse the inverted table range compare.
 define i32 @reuse_cmp1(i32 %x) {
+; CHECK-LABEL: @reuse_cmp1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[INVERTED_CMP:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT:    [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
+; CHECK-NEXT:    [[R_0:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 0
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[R_0]], 0
+; CHECK-NEXT:    [[DOTR_0:%.*]] = select i1 [[INVERTED_CMP]], i32 100, i32 [[R_0]]
+; CHECK-NEXT:    ret i32 [[DOTR_0]]
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 sw.bb: br label %sw.epilog
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

 if.then: br label %return
 if.end: br label %return
 return:
   %retval.0 = phi i32 [ 100, %if.then ], [ %r.0, %if.end ]
   ret i32 %retval.0
-; CHECK-LABEL: @reuse_cmp1(
-; CHECK: entry:
-; CHECK-NEXT: [[C:%.+]] = icmp ult i32 %x, 4
-; CHECK-NEXT: %inverted.cmp = xor i1 [[C]], true
-; CHECK:      [[R:%.+]] = select i1 %inverted.cmp, i32 100, i32 {{.*}}
-; CHECK-NEXT: ret i32 [[R]]
 }
 
 ; Reuse the table range compare.
 define i32 @reuse_cmp2(i32 %x) {
+; CHECK-LABEL: @reuse_cmp2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[X_:%.*]] = select i1 [[TMP0]], i32 [[X]], i32 4
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[X_]], 4
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = select i1 [[TMP0]], i32 [[X_]], i32 100
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 sw.bb: br label %sw.epilog
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

 if.then: br label %return
 if.end: br label %return
 return:
   %retval.0 = phi i32 [ %r.0, %if.then ], [ 100, %if.end ]
   ret i32 %retval.0
-; CHECK-LABEL: @reuse_cmp2(
-; CHECK: entry:
-; CHECK-NEXT: %0 = icmp ult i32 %x, 4
-; CHECK-NEXT: %x. = select i1 %0, i32 %x, i32 4
-; CHECK-NEXT: [[C:%.+]] = icmp ne i32 %x., 4
-; CHECK:      [[R:%.+]] = select i1 %0, i32 {{.*}}, i32 100
-; CHECK-NEXT: ret i32 [[R]]
 }
 
 ; Cannot reuse the table range compare, because the default value is the same
 ; as one of the case values.
 define i32 @no_reuse_cmp(i32 %x) {
+; CHECK-LABEL: @no_reuse_cmp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
+; CHECK-NEXT:    [[R_0:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 12
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[R_0]], 0
+; CHECK-NEXT:    [[R_0_:%.*]] = select i1 [[CMP]], i32 [[R_0]], i32 100
+; CHECK-NEXT:    ret i32 [[R_0_]]
+;
 entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 sw.bb: br label %sw.epilog
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

 if.then: br label %return
 if.end: br label %return
 return:
   %retval.0 = phi i32 [ %r.0, %if.then ], [ 100, %if.end ]
   ret i32 %retval.0
-; CHECK-LABEL: @no_reuse_cmp(
-; CHECK:  [[S:%.+]] = select
-; CHECK-NEXT:  %cmp = icmp ne i32 [[S]], 0
-; CHECK-NEXT:  [[R:%.+]] = select i1 %cmp, i32 [[S]], i32 100
-; CHECK-NEXT:  ret i32 [[R]]
 }
 
 ; Cannot reuse the table range compare, because the phi at the switch merge
 ; point is not dominated by the switch.
 define i32 @no_reuse_cmp2(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_reuse_cmp2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[EC:%.*]] = icmp ne i32 [[Y:%.*]], 0
+; CHECK-NEXT:    br i1 [[EC]], label [[SWITCH_ENTRY:%.*]], label [[SW_EPILOG:%.*]]
+; CHECK:       switch.entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 0
+; CHECK-NEXT:    br label [[SW_EPILOG]]
+; CHECK:       sw.epilog:
+; CHECK-NEXT:    [[R_0:%.*]] = phi i32 [ 100, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[SWITCH_ENTRY]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[R_0]], 0
+; CHECK-NEXT:    [[DOTR_0:%.*]] = select i1 [[CMP]], i32 100, i32 [[R_0]]
+; CHECK-NEXT:    ret i32 [[DOTR_0]]
+;
 entry:
   %ec = icmp ne i32 %y, 0
   br i1 %ec, label %switch.entry, label %sw.epilog
 switch.entry:
   switch i32 %x, label %sw.default [
-    i32 0, label %sw.bb
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-    i32 3, label %sw.bb3
   ]
 sw.bb: br label %sw.epilog
 sw.bb1: br label %sw.epilog
 sw.bb2: br label %sw.epilog
 sw.bb3: br label %sw.epilog

 if.then: br label %return
 if.end: br label %return
 return:
   %retval.0 = phi i32 [ 100, %if.then ], [ %r.0, %if.end ]
   ret i32 %retval.0
-; CHECK-LABEL: @no_reuse_cmp2(
-; CHECK:  %r.0 = phi
-; CHECK-NEXT:  %cmp = icmp eq i32 %r.0, 0
-; CHECK-NEXT:  [[R:%.+]] = select i1 %cmp
-; CHECK-NEXT:  ret i32 [[R]]
 }
 
 define void @pr20210(i8 %x, i1 %y) {
 ; %z has uses outside of its BB or the phi it feeds into,
 ; so doing a table lookup and jumping directly to while.cond would
 ; cause %z to cease dominating all its uses.
-
+; CHECK-LABEL: @pr20210(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[Y:%.*]], label [[SW:%.*]], label [[INTERMEDIATE:%.*]]
+; CHECK:       sw:
+; CHECK-NEXT:    switch i8 [[X:%.*]], label [[END:%.*]] [
+; CHECK-NEXT:    i8 7, label [[INTERMEDIATE]]
+; CHECK-NEXT:    i8 3, label [[INTERMEDIATE]]
+; CHECK-NEXT:    i8 2, label [[INTERMEDIATE]]
+; CHECK-NEXT:    i8 1, label [[INTERMEDIATE]]
+; CHECK-NEXT:    i8 0, label [[INTERMEDIATE]]
+; CHECK-NEXT:    ]
+; CHECK:       intermediate:
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[X]] to i32
+; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
+; CHECK:       while.cond:
+; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[Z]], [[INTERMEDIATE]] ], [ [[J:%.*]], [[WHILE_BODY:%.*]] ]
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i32 [[I]], 7
+; CHECK-NEXT:    br i1 [[B]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
+; CHECK:       while.body:
+; CHECK-NEXT:    [[J]] = add i32 [[I]], 1
+; CHECK-NEXT:    br label [[WHILE_COND]]
+; CHECK:       while.end:
+; CHECK-NEXT:    call void @exit(i32 [[Z]])
+; CHECK-NEXT:    unreachable
+; CHECK:       end:
+; CHECK-NEXT:    ret void
+;
 entry:
   br i1 %y, label %sw, label %intermediate
 
 sw:
   switch i8 %x, label %end [
-    i8 7, label %intermediate
-    i8 3, label %intermediate
-    i8 2, label %intermediate
-    i8 1, label %intermediate
-    i8 0, label %intermediate
   ]
 
 intermediate:
   %z = zext i8 %x to i32
   br label %while.cond

   call void @exit(i32 %z)
   unreachable
 
 end:
   ret void
-; CHECK-LABEL: @pr20210
-; CHECK: switch i8 %x
 }
 
 ; Make sure we do not crash due to trying to generate an unguarded
 ; lookup (since i3 can only hold values in the range of explicit
 ; values) and simultaneously trying to generate a branch to deal with
 ; the fact that we have holes in the range.
 define i32 @covered_switch_with_bit_tests(i3) {
+; CHECK-LABEL: @covered_switch_with_bit_tests(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i3 [[TMP0:%.*]], -4
+; CHECK-NEXT:    [[SWITCH_MASKINDEX:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i8
+; CHECK-NEXT:    [[SWITCH_SHIFTED:%.*]] = lshr i8 -61, [[SWITCH_MASKINDEX]]
+; CHECK-NEXT:    [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1
+; CHECK-NEXT:    br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[L6:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.covered_switch_with_bit_tests, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]]
+; CHECK-NEXT:    br label [[L6]]
+; CHECK:       l6:
+; CHECK-NEXT:    [[R:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ]
+; CHECK-NEXT:    ret i32 [[R]]
+;
 entry:
   switch i3 %0, label %l6 [
-    i3 -3, label %l5
-    i3 -4, label %l5
-    i3 3, label %l1
-    i3 2, label %l1
   ]
 
 l1: br label %l2
 
 l2:

 l5: br label %l2
 
 l6:
   %r = phi i32 [ %x, %l2 ], [ 0, %entry ]
   ret i32 %r
-; CHECK-LABEL: @covered_switch_with_bit_tests
-; CHECK: entry
-; CHECK-NEXT: switch
 }
 
 ; Speculation depth must be limited to avoid a zero-cost instruction cycle.
 
+define i32 @PR26308(i1 %B, i64 %load) {
 ; CHECK-LABEL: @PR26308(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[CLEANUP4:%.*]]
 ; CHECK:       cleanup4:
-; CHECK-NEXT:  br label %cleanup4
-
-define i32 @PR26308(i1 %B, i64 %load) {
+; CHECK-NEXT:    br label [[CLEANUP4]]
+;
 entry:
   br label %while.body
 
 while.body:
   br label %cleanup

 }
 
 declare void @throw(i1)
 
 define void @wineh_test(i64 %val) personality i32 (...)* @__CxxFrameHandler3 {
+; CHECK-LABEL: @wineh_test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    invoke void @throw(i1 false)
+; CHECK-NEXT:    to label [[UNREACHABLE:%.*]] unwind label [[CLEANUP1:%.*]]
+; CHECK:       unreachable:
+; CHECK-NEXT:    unreachable
+; CHECK:       cleanup1:
+; CHECK-NEXT:    [[CLEANUPPAD1:%.*]] = cleanuppad within none []
+; CHECK-NEXT:    switch i64 [[VAL:%.*]], label [[CLEANUPDONE2:%.*]] [
+; CHECK-NEXT:    i64 0, label [[CLEANUPDONE1:%.*]]
+; CHECK-NEXT:    i64 1, label [[CLEANUPDONE1]]
+; CHECK-NEXT:    i64 6, label [[CLEANUPDONE1]]
+; CHECK-NEXT:    ]
+; CHECK:       cleanupdone1:
+; CHECK-NEXT:    cleanupret from [[CLEANUPPAD1]] unwind label [[CLEANUP2:%.*]]
+; CHECK:       cleanupdone2:
+; CHECK-NEXT:    cleanupret from [[CLEANUPPAD1]] unwind label [[CLEANUP2]]
+; CHECK:       cleanup2:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i1 [ true, [[CLEANUPDONE1]] ], [ false, [[CLEANUPDONE2]] ]
+; CHECK-NEXT:    [[CLEANUPPAD2:%.*]] = cleanuppad within none []
+; CHECK-NEXT:    call void @throw(i1 [[PHI]]) [ "funclet"(token [[CLEANUPPAD2]]) ]
+; CHECK-NEXT:    unreachable
+;
 entry:
   invoke void @throw(i1 false)
-          to label %unreachable unwind label %cleanup1
 
 unreachable:
   unreachable
 
 cleanup1:
   %cleanuppad1 = cleanuppad within none []
   switch i64 %val, label %cleanupdone2 [
-    i64 0, label %cleanupdone1
-    i64 1, label %cleanupdone1
-    i64 6, label %cleanupdone1
   ]
 
 cleanupdone1:
   cleanupret from %cleanuppad1 unwind label %cleanup2
 

   %cleanuppad2 = cleanuppad within none []
   call void @throw(i1 %phi) [ "funclet"(token %cleanuppad2) ]
   unreachable
 }
 
-; CHECK-LABEL: @wineh_test(
-; CHECK: entry:
-; CHECK:   invoke void @throw(i1 false)
-; CHECK:           to label %[[unreachable:.*]] unwind label %[[cleanup1:.*]]
-
-; CHECK: [[unreachable]]:
-; CHECK:   unreachable
-
-; CHECK: [[cleanup1]]:
-; CHECK:   %[[cleanuppad1:.*]] = cleanuppad within none []
-; CHECK:   switch i64 %val, label %[[cleanupdone2:.*]] [
-; CHECK:     i64 0, label %[[cleanupdone1:.*]]
-; CHECK:     i64 1, label %[[cleanupdone1]]
-; CHECK:     i64 6, label %[[cleanupdone1]]
-; CHECK:   ]
-
-; CHECK: [[cleanupdone1]]:
-; CHECK:   cleanupret from %[[cleanuppad1]] unwind label %[[cleanup2:.*]]
-
-; CHECK: [[cleanupdone2]]:
-; CHECK:   cleanupret from %[[cleanuppad1]] unwind label %[[cleanup2]]
-
-; CHECK: [[cleanup2]]:
-; CHECK:   %[[phi:.*]] = phi i1 [ true, %[[cleanupdone1]] ], [ false, %[[cleanupdone2]] ]
-; CHECK:   %[[cleanuppad2:.*]] = cleanuppad within none []
-; CHECK:   call void @throw(i1 %[[phi]]) [ "funclet"(token %[[cleanuppad2]]) ]
-; CHECK:   unreachable
-
 declare i32 @__CxxFrameHandler3(...)

test/Transforms/SimplifyCFG/switch-dead-default.ll

-; RUN: opt %s -S -simplifycfg | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -S -passes='simplify-cfg<switch-to-lookup>' | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 declare void @foo(i32)
 
 define void @test(i1 %a) {
-; CHECK-LABEL: @test
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    br i1 [[A:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   switch i1 %a, label %default [i1 1, label %true
-                                i1 0, label %false]
 true:
   call void @foo(i32 1)
   ret void
 false:
   call void @foo(i32 3)
   ret void
 default:
   call void @foo(i32 2)
   ret void
-}  
+}
 
 define void @test2(i2 %a) {
-; CHECK-LABEL: @test2
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT1:%.*]] [
+; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
+; CHECK-NEXT:    i2 -1, label [[CASE3:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       case2:
+; CHECK-NEXT:    tail call void @foo(i32 2)
+; CHECK-NEXT:    ret void
+; CHECK:       case3:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+; CHECK:       default1:
+; CHECK-NEXT:    unreachable
+;
   switch i2 %a, label %default [i2 0, label %case0
-                                i2 1, label %case1
-                                i2 2, label %case2
-                                i2 3, label %case3]
 case0:
   call void @foo(i32 0)
   ret void
 case1:
   call void @foo(i32 1)

   ret void
 case3:
   call void @foo(i32 3)
   ret void
 default:
-; CHECK-LABEL: default1:
-; CHECK-NEXT: unreachable
   call void @foo(i32 4)
   ret void
-}  
+}
 
 ; This one is a negative test - we know the value of the default,
 ; but that's about it
 define void @test3(i2 %a) {
-; CHECK-LABEL: @test3
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       case2:
+; CHECK-NEXT:    tail call void @foo(i32 2)
+; CHECK-NEXT:    ret void
+; CHECK:       default:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+;
   switch i2 %a, label %default [i2 0, label %case0
-                                i2 1, label %case1
-                                i2 2, label %case2]
 
 case0:
   call void @foo(i32 0)
   ret void
 case1:

   ret void
 case2:
   call void @foo(i32 2)
   ret void
 default:
-; CHECK-LABEL: default:
-; CHECK-NEXT: call void @foo
   call void @foo(i32 0)
   ret void
-}  
+}
 
 ; Negative test - check for possible overflow when computing
 ; number of possible cases.
 define void @test4(i128 %a) {
-; CHECK-LABEL: @test4
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i128 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i128 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       default:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+;
   switch i128 %a, label %default [i128 0, label %case0
-                                  i128 1, label %case1]
 
 case0:
   call void @foo(i32 0)
   ret void
 case1:
   call void @foo(i32 1)
   ret void
 default:
-; CHECK-LABEL: default:
-; CHECK-NEXT: call void @foo
   call void @foo(i32 0)
   ret void
-}  
+}
 
 ; All but one bit known zero
 define void @test5(i8 %a) {
-; CHECK-LABEL: @test5
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
-  %cmp = icmp ult i8 %a, 2 
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], 1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
+  %cmp = icmp ult i8 %a, 2
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 1, label %true
-                                i8 0, label %false]
 true:
   call void @foo(i32 1)
   ret void
 false:
   call void @foo(i32 3)
   ret void
 default:
   call void @foo(i32 2)
   ret void
-} 
+}
 
 ;; All but one bit known one
 define void @test6(i8 %a) {
-; CHECK-LABEL: @test6
-; CHECK: @llvm.assume
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[A:%.*]], -3
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], -1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   %and = and i8 %a, 254
-  %cmp = icmp eq i8 %and, 254 
+  %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false]
 true:
   call void @foo(i32 1)
   ret void
 false:
   call void @foo(i32 3)

 }
 
 ; Check that we can eliminate both dead cases and dead defaults
 ; within a single run of simplify-cfg
 define void @test7(i8 %a) {
-; CHECK-LABEL: @test7
-; CHECK: @llvm.assume
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[A:%.*]], -3
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], -1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   %and = and i8 %a, 254
-  %cmp = icmp eq i8 %and, 254 
+  %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false
-                                i8 0, label %also_dead]
 true:
   call void @foo(i32 1)
   ret void
 false:
   call void @foo(i32 3)

   ret void
 }
 
 ;; All but one bit known undef
 ;; Note: This is currently testing an optimization which doesn't trigger. The
-;; case this is protecting against is that a bit could be assumed both zero 
+;; case this is protecting against is that a bit could be assumed both zero
 ;; *or* one given we know it's undef.  ValueTracking doesn't do this today,
 ;; but it doesn't hurt to confirm.
 define void @test8(i8 %a) {
 ; CHECK-LABEL: @test8(
-; CHECK: switch i8
+; CHECK-NEXT:    unreachable
+;
   %and = and i8 %a, 254
   %cmp = icmp eq i8 %and, undef
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false]
 true:
   call void @foo(i32 1)
   ret void
 false:
   call void @foo(i32 3)

test/Transforms/SimplifyCFG/switch-genfori8.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s | FileCheck %s
+; Using a Zig driver https://gist.github.com/shawnl/8137f62f7dbcfd539f6cf1925387cd38
+;after-patch, covered lookup table: 509.8MiB/sec
+;lookup table, not covered, only valid digits to prime the branch predictor: 437.8MiB/sec
+;lookup table, not covered, random bytes: 242.0MiB/sec
+;before-patch, no lookup table: 205.4MiB/sec
+
+; ModuleID = 'chartodigit.c'
+source_filename = "chartodigit.c"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+; Function Attrs: norecurse nounwind readnone uwtable
+define dso_local zeroext i8 @char_to_digit(i8 zeroext) local_unnamed_addr #0 {
+; CHECK-LABEL: @char_to_digit(
+; CHECK-NEXT:    switch i8 [[TMP0:%.*]], label [[TMP17:%.*]] [
+; CHECK-NEXT:    i8 48, label [[TMP18:%.*]]
+; CHECK-NEXT:    i8 49, label [[TMP2:%.*]]
+; CHECK-NEXT:    i8 50, label [[TMP3:%.*]]
+; CHECK-NEXT:    i8 51, label [[TMP4:%.*]]
+; CHECK-NEXT:    i8 52, label [[TMP5:%.*]]
+; CHECK-NEXT:    i8 53, label [[TMP6:%.*]]
+; CHECK-NEXT:    i8 54, label [[TMP7:%.*]]
+; CHECK-NEXT:    i8 55, label [[TMP8:%.*]]
+; CHECK-NEXT:    i8 56, label [[TMP9:%.*]]
+; CHECK-NEXT:    i8 57, label [[TMP10:%.*]]
+; CHECK-NEXT:    i8 97, label [[TMP11:%.*]]
+; CHECK-NEXT:    i8 98, label [[TMP12:%.*]]
+; CHECK-NEXT:    i8 99, label [[TMP13:%.*]]
+; CHECK-NEXT:    i8 100, label [[TMP14:%.*]]
+; CHECK-NEXT:    i8 101, label [[TMP15:%.*]]
+; CHECK-NEXT:    i8 102, label [[TMP16:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       2:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       3:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       4:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       5:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       6:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       7:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       8:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       9:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       10:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       11:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       12:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       13:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       14:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       15:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       16:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       17:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       18:
+; CHECK-NEXT:    [[TMP19:%.*]] = phi i8 [ -1, [[TMP17]] ], [ 15, [[TMP16]] ], [ 14, [[TMP15]] ], [ 13, [[TMP14]] ], [ 12, [[TMP13]] ], [ 11, [[TMP12]] ], [ 10, [[TMP11]] ], [ 9, [[TMP10]] ], [ 8, [[TMP9]] ], [ 7, [[TMP8]] ], [ 6, [[TMP7]] ], [ 5, [[TMP6]] ], [ 4, [[TMP5]] ], [ 3, [[TMP4]] ], [ 2, [[TMP3]] ], [ 1, [[TMP2]] ], [ 0, [[TMP1:%.*]] ]
+; CHECK-NEXT:    ret i8 [[TMP19]]
+;
+  switch i8 %0, label %17 [
+  i8 48, label %18
+  i8 49, label %2
+  i8 50, label %3
+  i8 51, label %4
+  i8 52, label %5
+  i8 53, label %6
+  i8 54, label %7
+  i8 55, label %8
+  i8 56, label %9
+  i8 57, label %10
+  i8 97, label %11
+  i8 98, label %12
+  i8 99, label %13
+  i8 100, label %14
+  i8 101, label %15
+  i8 102, label %16
+  ]
+
+; <label>:2:                                      ; preds = %1
+  br label %18
+
+; <label>:3:                                      ; preds = %1
+  br label %18
+
+; <label>:4:                                      ; preds = %1
+  br label %18
+
+; <label>:5:                                      ; preds = %1
+  br label %18
+
+; <label>:6:                                      ; preds = %1
+  br label %18
+
+; <label>:7:                                      ; preds = %1
+  br label %18
+
+; <label>:8:                                      ; preds = %1
+  br label %18
+
+; <label>:9:                                      ; preds = %1
+  br label %18
+
+; <label>:10:                                     ; preds = %1
+  br label %18
+
+; <label>:11:                                     ; preds = %1
+  br label %18
+
+; <label>:12:                                     ; preds = %1
+  br label %18
+
+; <label>:13:                                     ; preds = %1
+  br label %18
+
+; <label>:14:                                     ; preds = %1
+  br label %18
+
+; <label>:15:                                     ; preds = %1
+  br label %18
+
+; <label>:16:                                     ; preds = %1
+  br label %18
+
+; <label>:17:                                     ; preds = %1
+  br label %18
+
+; <label>:18:                                     ; preds = %1, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5, %4, %3, %2
+  %19 = phi i8 [ -1, %17 ], [ 15, %16 ], [ 14, %15 ], [ 13, %14 ], [ 12, %13 ], [ 11, %12 ], [ 10, %11 ], [ 9, %10 ], [ 8, %9 ], [ 7, %8 ], [ 6, %7 ], [ 5, %6 ], [ 4, %5 ], [ 3, %4 ], [ 2, %3 ], [ 1, %2 ], [ 0, %1 ]
+  ret i8 %19
+}
+
+attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 8.0.0-3 (tags/RELEASE_800/final)"}

test/Transforms/SimplifyCFG/switch-masked-bits.ll

 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 
 define i32 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  a:
-; CHECK-NEXT:    [[I:%.*]] = shl i32 %x, 1
+; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
-; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0
-; CHECK-NEXT:    ret i32 [[DOT]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 5, i32 0
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ;
   %i = shl i32 %x, 1
   switch i32 %i, label %a [
   i32 21, label %b
   i32 24, label %c

 ; We're sign extending an 8-bit value.
 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
-; CHECK:         switch i32
-; CHECK-DAG:     i32 -128, label %a
-; CHECK-DAG:     i32 -1, label %a
-; CHECK-DAG:     i32  0, label %a
-; CHECK-DAG:     i32  127, label %a
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[A:%.*]]
+; CHECK-NEXT:    i32 127, label [[A]]
+; CHECK-NEXT:    i32 -128, label [[A]]
+; CHECK-NEXT:    i32 -1, label [[A]]
 ; CHECK-NEXT:    ]
+; CHECK:       a:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
+; CHECK-NEXT:    ret i1 [[MERGE]]
+; CHECK:       default:
+; CHECK-NEXT:    br label [[A]]
 ;
 entry:
   %sext = sext i8 %condition to i32
   switch i32 %sext, label %default [
   i32 -2147483648, label %a

test/Transforms/SimplifyCFG/switch-on-const-select.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -S | FileCheck -enable-var-scope %s
 
 ; Test basic folding to a conditional branch.
 define i32 @foo(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]]
+; CHECK:       switch:
+; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
+; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B]]
+; CHECK:       a:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret i32 1
+; CHECK:       b:
+; CHECK-NEXT:    [[RETVAL:%.*]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    tail call void @bees.b() #0
+; CHECK-NEXT:    ret i32 [[RETVAL]]
+;
 entry:
-    %eq = icmp eq i64 %x, %y
-    br i1 %eq, label %b, label %switch
 switch:
-    %lt = icmp slt i64 %x, %y
-; CHECK: br i1 %lt, label %a, label %b
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %b
-        i32 2, label %b
-    ]
 a:
-    tail call void @bees.a() nounwind
-    ret i32 1
-; CHECK: b:
-; CHECK-NEXT: %retval = phi i32 [ 0, %switch ], [ 2, %entry ]
 b:
-    %retval = phi i32 [0, %switch], [0, %switch], [2, %entry]
-    tail call void @bees.b() nounwind
-    ret i32 %retval
-; CHECK-NOT: bees:
 bees:
-    tail call void @llvm.trap() nounwind
-    unreachable
 }
 
 ; Test basic folding to an unconditional branch.
 define i32 @bar(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bar(
-entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[$NUW:#[0-9]+]]
-; CHECK-NEXT: ret i32 0
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %b
-        i32 2, label %a
-    ]
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret i32 0
+;
+entry:
 a:
-    %retval = phi i32 [0, %entry], [0, %entry], [1, %b]
-    tail call void @bees.a() nounwind
-    ret i32 0
 b:
-    tail call void @bees.b() nounwind
-    br label %a
 bees:
-    tail call void @llvm.trap() nounwind
-    unreachable
 }
 
 ; Test the edge case where both values from the select are the default case.
 define void @bazz(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bazz(
-entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.b() [[$NUW]]
-; CHECK-NEXT: ret void
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 10, i32 12
-    switch i32 %qux, label %b [
-        i32 0, label %a
-        i32 1, label %bees
-        i32 2, label %bees
-    ]
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.b() #0
+; CHECK-NEXT:    ret void
+;
+entry:
 a:
-    tail call void @bees.a() nounwind
-    ret void
 b:
-    tail call void @bees.b() nounwind
-    ret void
 bees:
-    tail call void @llvm.trap()
-    unreachable
 }
 
 ; Test the edge case where both values from the select are equal.
 define void @quux(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @quux(
-entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[$NUW]]
-; CHECK-NEXT: ret void
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 0, i32 0
-    switch i32 %qux, label %b [
-        i32 0, label %a
-        i32 1, label %bees
-        i32 2, label %bees
-    ]
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret void
+;
+entry:
 a:
-    tail call void @bees.a() nounwind
-    ret void
 b:
-    tail call void @bees.b() nounwind
-    ret void
 bees:
-    tail call void @llvm.trap()
-    unreachable
 }
 
 ; A final test, for phi node munging.
 define i32 @xyzzy(i64 %x, i64 %y) {
 ; CHECK-LABEL: @xyzzy(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1
+; CHECK-NEXT:    [[VAL:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    ret i32 [[VAL]]
+;
 entry:
-    %eq = icmp eq i64 %x, %y
-    br i1 %eq, label %r, label %cont
 cont:
-; CHECK: %lt = icmp slt i64 %x, %y
-    %lt = icmp slt i64 %x, %y
-; CHECK-NEXT: select i1 %lt, i32 -1, i32 1
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %r
-        i32 2, label %r
-    ]
 r:
-    %val = phi i32 [0, %entry], [1, %cont], [1, %cont]
-    ret i32 %val
 a:
-    ret i32 -1
-; CHECK-NOT: bees:
 bees:
-    tail call void @llvm.trap()
-    unreachable
 }
 
 declare void @llvm.trap() nounwind noreturn
 declare void @bees.a() nounwind
 declare void @bees.b() nounwind
 
-; CHECK: attributes [[$NUW]] = { nounwind }
 ; CHECK: attributes #1 = { cold noreturn nounwind }

test/Transforms/SimplifyCFG/switch-range-to-icmp.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -simplifycfg -S | FileCheck %s
 
 declare i32 @f(i32)
 
 define i32 @basic(i32 %x) {
-; CHECK-LABEL: @basic
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %default
+; CHECK-LABEL: @basic(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[DEFAULT:%.*]]
+; CHECK:       default:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   switch i32 %x, label %default [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
   ]
 default:
   %0 = call i32 @f(i32 0)
   ret i32 %0
 a:

   ret i32 %1
 }
 
 
 define i32 @unreachable(i32 %x) {
-; CHECK-LABEL: @unreachable
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %b
+; CHECK-LABEL: @unreachable(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       b:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   switch i32 %x, label %unreachable [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
-    i32 10, label %b
-    i32 20, label %b
-    i32 30, label %b
-    i32 40, label %b
   ]
 unreachable:
   unreachable
 a:
   %0 = call i32 @f(i32 0)

   ret i32 %1
 }
 
 
 define i32 @unreachable2(i32 %x) {
-; CHECK-LABEL: @unreachable2
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %b
+; CHECK-LABEL: @unreachable2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       b:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   ; Note: folding the most popular case destination into the default
   ; would prevent switch-to-icmp here.
   switch i32 %x, label %unreachable [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
-    i32 10, label %b
-    i32 20, label %b
   ]
 unreachable:
   unreachable
 a:
   %0 = call i32 @f(i32 0)

test/Transforms/SimplifyCFG/switch-simplify-range.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+attributes #0 = { "no-jump-tables"="false" }
+
+define i64 @switch_common_right_bits(i8 %a) #0  {
+; CHECK-LABEL: @switch_common_right_bits(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i8 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i8 123, label [[SWITCHPRONG:%.*]]
+; CHECK-NEXT:    i8 125, label [[SWITCHPRONG1:%.*]]
+; CHECK-NEXT:    i8 127, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i8 -127, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i8 -125, label [[SWITCHPRONG4:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 10, [[ENTRY:%.*]] ], [ 6, [[SWITCHPRONG]] ], [ 3, [[SWITCHPRONG1]] ], [ 4, [[SWITCHPRONG2]] ], [ 2, [[SWITCHPRONG3]] ], [ 1, [[SWITCHPRONG4]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng1:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng4:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 123, label %SwitchProng
+  i8 125, label %SwitchProng1
+  i8 127, label %SwitchProng2
+  i8 129, label %SwitchProng3
+  i8 131, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i64 10
+SwitchProng:                                      ; preds = %Entry
+  ret i64 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i64 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 4
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 2
+SwitchProng4:                                     ; preds = %Entry
+  ret i64 1
+}
+
+define i64 @switch_clz1(i16 %a) optsize #0  {
+; CHECK-LABEL: @switch_clz1(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i16 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i16 2, label [[SWITCHPRONG:%.*]]
+; CHECK-NEXT:    i16 4, label [[SWITCHPRONG1:%.*]]
+; CHECK-NEXT:    i16 8, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i16 1, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i16 64, label [[SWITCHPRONG6:%.*]]
+; CHECK-NEXT:    i16 128, label [[SWITCHPRONG7:%.*]]
+; CHECK-NEXT:    i16 16, label [[SWITCHPRONG5:%.*]]
+; CHECK-NEXT:    i16 32, label [[SWITCHPRONG4:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 10, [[ENTRY:%.*]] ], [ 6, [[SWITCHPRONG]] ], [ 3, [[SWITCHPRONG1]] ], [ 35, [[SWITCHPRONG2]] ], [ 31, [[SWITCHPRONG3]] ], [ 53, [[SWITCHPRONG4]] ], [ 51, [[SWITCHPRONG5]] ], [ 41, [[SWITCHPRONG6]] ], [ 34, [[SWITCHPRONG7]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng1:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng4:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng5:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng6:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng7:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+;
+Entry:
+  switch i16 %a, label %SwitchElse [
+  i16 2, label %SwitchProng
+  i16 4, label %SwitchProng1
+  i16 8, label %SwitchProng2
+  i16 1, label %SwitchProng3
+  i16 64, label %SwitchProng6
+  i16 128, label %SwitchProng7
+  i16 16, label %SwitchProng5
+  i16 32, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i64 10
+SwitchProng:                                      ; preds = %Entry
+  ret i64 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i64 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 35
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 31
+SwitchProng4:                                     ; preds = %Entry
+  ret i64 53
+SwitchProng5:                                     ; preds = %Entry
+  ret i64 51
+SwitchProng6:                                     ; preds = %Entry
+  ret i64 41
+SwitchProng7:                                     ; preds = %Entry
+  ret i64 34
+}
+
+define i64 @switch_clz2(i8 %a) optsize #0  {
+; CHECK-LABEL: @switch_clz2(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i8 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i8 -128, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i8 64, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i8 32, label [[SWITCHPRONG6:%.*]]
+; CHECK-NEXT:    i8 1, label [[SWITCHPRONG7:%.*]]
+; CHECK-NEXT:    i8 0, label [[SWITCHPRONG5:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 35, [[ENTRY:%.*]] ], [ 31, [[SWITCHPRONG3]] ], [ 41, [[SWITCHPRONG6]] ], [ 40, [[SWITCHPRONG5]] ], [ 43, [[SWITCHPRONG7]] ], [ 12, [[SWITCHELSE]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng6:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng5:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng7:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 128, label %SwitchProng2
+  i8 64, label %SwitchProng3
+  i8 32, label %SwitchProng6
+  i8 1, label %SwitchProng7
+  i8 0, label %SwitchProng5
+  ]
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 35
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 31
+SwitchProng6:                                     ; preds = %Entry
+  ret i64 41
+SwitchProng5:                                     ; preds = %Entry
+  ret i64 40
+SwitchProng7:                                     ; preds = %Entry
+  ret i64 43
+SwitchElse:                                     ; preds = %Entry
+  ret i64 12
+}
+
+;Must check that the default was filled in at index 0 as happened here:
+;@switch.table.switch_not_normalized_to_start_at_zero = private unnamed_addr constant [6 x i16] [i16 10, i16 7, i16 3, i16 1, i16 6, i16 8], align 2
+define i16 @switch_not_normalized_to_start_at_zero(i8 %a) #0  {
+; CHECK-LABEL: @switch_not_normalized_to_start_at_zero(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i8 [[A:%.*]], 1
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 5
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SWITCHELSE:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i16], [5 x i16]* @switch.table.switch_not_normalized_to_start_at_zero, i32 0, i8 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i16, i16* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i16 [[SWITCH_LOAD]]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    ret i16 10
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 4, label %SwitchProng
+  i8 2, label %SwitchProng1
+  i8 1, label %SwitchProng2
+  i8 3, label %SwitchProng3
+  i8 5, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i16 10
+SwitchProng:                                      ; preds = %Entry
+  ret i16 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i16 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i16 7
+SwitchProng3:                                     ; preds = %Entry
+  ret i16 1
+SwitchProng4:                                     ; preds = %Entry
+  ret i16 8
+}

test/Transforms/SimplifyCFG/switch_create-custom-dl.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 target datalayout="p:40:64:64:32"
 
 declare void @foo1()
 
 declare void @foo2()
 
 define void @test1(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1(
-; CHECK:  switch i32 %V, label %F [
-; CHECK:    i32 17, label %T
-; CHECK:    i32 4, label %T
-; CHECK:  ]
 }
 
 define void @test1_ptr(i32* %V) {
-        %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
-        %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1_ptr(
+; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
+  %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr(
-; DL:  %magicptr = ptrtoint i32* %V to i32
-; DL:  switch i32 %magicptr, label %F [
-; DL:    i32 17, label %T
-; DL:    i32 4, label %T
-; DL:  ]
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
-        %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
-        %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1_ptr_as1(
+; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
+  %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr_as1(
-; DL:  %magicptr = ptrtoint i32 addrspace(1)* %V to i16
-; DL:  switch i16 %magicptr, label %F [
-; DL:    i16 17, label %T
-; DL:    i16 4, label %T
-; DL:  ]
 }
 
 define void @test2(i32 %V) {
-        %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
-        %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 17, label [[F:%.*]]
+; CHECK-NEXT:    i32 4, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
+  %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test2(
-; CHECK:  switch i32 %V, label %T [
-; CHECK:    i32 17, label %F
-; CHECK:    i32 4, label %F
-; CHECK:  ]
 }
 
 define void @test3(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        br i1 %C1, label %T, label %N
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 4, label [[T:%.*]]
+; CHECK-NEXT:    i32 17, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  br i1 %C1, label %T, label %N
 N:              ; preds = %0
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %N
-        call void @foo2( )
-        ret void
 
-; CHECK-LABEL: @test3(
-; CHECK: switch i32 %V, label %F [
-; CHECK:     i32 4, label %T
-; CHECK:     i32 17, label %T
-; CHECK:   ]
 }
 
 
 
 define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   %cmp = icmp eq i8 %c, 62
   br i1 %cmp, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry

 lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK-LABEL: @test4(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   switch i8 %c, label %lor.rhs [
-    i8 62, label %lor.end
-    i8 34, label %lor.end
-    i8 92, label %lor.end
   ]
 
 lor.rhs:                                          ; preds = %entry
   %V = icmp eq i8 %c, 92
   br label %lor.end
 
 lor.end:                                          ; preds = %entry, %entry, %entry, %lor.rhs
   %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
-; CHECK-LABEL: @test5(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 
 define i1 @test6({ i32, i32 }* %I) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]]
+; CHECK-NEXT:    [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
 entry:
-        %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
-        %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
-        %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
-        br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
 shortcirc_next.0:               ; preds = %entry
-        %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
-        br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
 shortcirc_next.1:               ; preds = %shortcirc_next.0
-        %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
-        br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
 shortcirc_next.2:               ; preds = %shortcirc_next.1
-        %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
-        br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
 shortcirc_next.3:               ; preds = %shortcirc_next.2
-        %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
-        br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
 shortcirc_next.4:               ; preds = %shortcirc_next.3
-        %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
-        br label %UnifiedReturnBlock
 shortcirc_done.4:               ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
-        br label %UnifiedReturnBlock
 UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
-        %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
-        ret i1 %UnifiedRetVal
 
-; CHECK-LABEL: @test6(
-; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
-; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret void
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99

   ret void
 
 if.end:                                           ; preds = %entry
   ret void
 
-; CHECK-LABEL: @test7(
-; CHECK:   %cmp = icmp ult i32 %x, 32
-; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
+; CHECK:       N:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 0
+;
 entry:
   br i1 %C, label %N, label %if.then
 N:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97

   ret i32 %A
 
 if.end:                                           ; preds = %entry
   ret i32 0
 
-; CHECK-LABEL: @test8(
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
-; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
 ;; This is "Example 7" from http://blog.regehr.org/archives/320
 define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    i8 62, label [[LOR_END]]
+; CHECK-NEXT:    i8 60, label [[LOR_END]]
+; CHECK-NEXT:    i8 59, label [[LOR_END]]
+; CHECK-NEXT:    i8 58, label [[LOR_END]]
+; CHECK-NEXT:    i8 46, label [[LOR_END]]
+; CHECK-NEXT:    i8 44, label [[LOR_END]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 39, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    [[CONV46:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[CONV46]]
+;
 entry:
   %cmp = icmp ult i8 %c, 33
   br i1 %cmp, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry

 lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
   %0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
   %conv46 = zext i1 %0 to i32
   ret i32 %conv46
 
-; CHECK-LABEL: @test9(
-; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
-
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 51, label [[F]]
+; CHECK-NEXT:    i32 0, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       F:
+; CHECK-NEXT:    br label [[T]]
+;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
   %D = and i1 %C, %Cond
   br i1 %D, label %T, label %F
 T:
   ret i32 123
 F:
   ret i32 324
 
-; CHECK-LABEL: @test10(
-; CHECK:  br i1 %Cond, label %switch.early.test, label %F
-; CHECK:switch.early.test:
-; CHECK:  switch i32 %mode, label %T [
-; CHECK:    i32 51, label %F
-; CHECK:    i32 0, label %F
-; CHECK:  ]
 }
 
 ; PR8780
 define i32 @test11(i32 %bar) nounwind {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 55, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 53, label [[RETURN]]
+; CHECK-NEXT:    i32 35, label [[RETURN]]
+; CHECK-NEXT:    i32 24, label [[RETURN]]
+; CHECK-NEXT:    i32 23, label [[RETURN]]
+; CHECK-NEXT:    i32 12, label [[RETURN]]
+; CHECK-NEXT:    i32 4, label [[RETURN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.end:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   %cmp = icmp eq i32 %bar, 4
   %cmp2 = icmp eq i32 %bar, 35
   %or.cond = or i1 %cmp, %cmp2
   %cmp5 = icmp eq i32 %bar, 53

 
 return:                                           ; preds = %if.end, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @test11(
-; CHECK: switch i32 %bar, label %if.end [
-; CHECK:   i32 55, label %return
-; CHECK:   i32 53, label %return
-; CHECK:   i32 35, label %return
-; CHECK:   i32 24, label %return
-; CHECK:   i32 23, label %return
-; CHECK:   i32 12, label %return
-; CHECK:   i32 4, label %return
-; CHECK: ]
 }
 
 define void @test12() nounwind {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK:       bb55.us.us:
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK:       malformed:
+; CHECK-NEXT:    ret void
+;
 entry:
   br label %bb49.us.us
 
 bb49.us.us:
   %A = icmp eq i32 undef, undef

 bb55.us.us:
   br label %bb48.us.us
 
 malformed:
   ret void
-; CHECK-LABEL: @test12(
 
 }
 
 ; test13 - handle switch formation with ult.
 define void @test13(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 2
   br i1 %cmp, label %if.then, label %lor.lhs.false3
 
 lor.lhs.false3:                                   ; preds = %lor.lhs.false

   call void @foo1() noredzone
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test13(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; test14 - handle switch formation with ult.
 define void @test14(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 2, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ugt i32 %x, 2
   br i1 %cmp, label %lor.lhs.false3, label %if.then
 
 lor.lhs.false3:                                   ; preds = %lor.lhs.false

   call void @foo1() noredzone
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test14(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; Don't crash on ginormous ranges.
 define void @test15(i128 %x) nounwind {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:  if.end:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ugt i128 %x, 2
   br i1 %cmp, label %if.end, label %lor.false
 
 lor.false:
   %cmp2 = icmp ne i128 %x, 100000000000000000000

   br label %if.end
 
 if.end:
   ret void
 
-; CHECK-LABEL: @test15(
-; CHECK-NOT: switch
-; CHECK: ret void
 }
 
 ; PR8675
 ; rdar://5134905
 define zeroext i1 @test16(i32 %x) nounwind {
-entry:
 ; CHECK-LABEL: @test16(
-; CHECK: %x.off = add i32 %x, -1
-; CHECK: %switch = icmp ult i32 %x.off, 3
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
+entry:
   %cmp.i = icmp eq i32 %x, 1
   br i1 %cmp.i, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:
   %cmp.i2 = icmp eq i32 %x, 2

   ret i1 %0
 }
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
+; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK:       lor.lhs.false8:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
   br i1 %or.cond775, label %lor.lhs.false8, label %return
 

   ret void
 
 return:
   ret void
 
-; CHECK-LABEL: @test17(
-; CHECK-NOT: switch.early.test
-; CHECK-NOT: switch i32
-; CHECK: ret void
 }
 
 define void @test18(i32 %arg) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]]
+; CHECK:       bb19:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    br label [[BB20]]
+; CHECK:       bb20:
+; CHECK-NEXT:    ret void
+;
 bb:
   %tmp = and i32 %arg, -2
   %tmp1 = icmp eq i32 %tmp, 8
   %tmp2 = icmp eq i32 %arg, 10
   %tmp3 = or i1 %tmp1, %tmp2

   br label %bb20
 
 bb20:                                             ; preds = %bb19, %bb8
   ret void
 
-; CHECK-LABEL: @test18(
-; CHECK: %arg.off = add i32 %arg, -8
-; CHECK: icmp ult i32 %arg.off, 11
 }
 
 define void @PR26323(i1 %tobool23, i32 %tmp3) {
+; CHECK-LABEL: @PR26323(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0
+; CHECK-NEXT:    [[NEG14:%.*]] = and i32 [[TMP3]], -2
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]]
+; CHECK-NEXT:    [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]]
+; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]]
+; CHECK:       if.then27:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    unreachable
+; CHECK:       if.end29:
+; CHECK-NEXT:    ret void
+;
 entry:
   %tobool5 = icmp ne i32 %tmp3, 0
   %neg14 = and i32 %tmp3, -2
   %cmp17 = icmp ne i32 %neg14, -1
   %or.cond = and i1 %tobool5, %tobool23

 
 if.end29:                                         ; preds = %entry
   ret void
 }
 
-; CHECK-LABEL: define void @PR26323(
-; CHECK:  %tobool5 = icmp ne i32 %tmp3, 0
-; CHECK:  %neg14 = and i32 %tmp3, -2
-; CHECK:  %cmp17 = icmp ne i32 %neg14, -1
-; CHECK:  %or.cond = and i1 %tobool5, %tobool23
-; CHECK:  %or.cond1 = and i1 %cmp17, %or.cond
-; CHECK:  br i1 %or.cond1, label %if.end29, label %if.then27
-
-; Form a switch when and'ing a negated power of two
-; CHECK-LABEL: define void @test19
-; CHECK: switch i32 %arg, label %else [
-; CHECK: i32 32, label %if
-; CHECK: i32 13, label %if
-; CHECK: i32 12, label %if
 define void @test19(i32 %arg) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    i32 32, label [[IF:%.*]]
+; CHECK-NEXT:    i32 13, label [[IF]]
+; CHECK-NEXT:    i32 12, label [[IF]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
-; CHECK-LABEL: define void @test20
-; CHECK-NOT: switch
-; CHECK: ret void
 define void @test20(i32 %arg) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Form a switch when or'ing a power of two
-; CHECK-LABEL: define void @test21
-; CHECK: i32 32, label %else
-; CHECK: i32 13, label %else
-; CHECK: i32 12, label %else
 define void @test21(i32 %arg) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
+; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
+; CHECK-NEXT:    i32 13, label [[ELSE]]
+; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
-; CHECK-LABEL: define void @test22
-; CHECK-NOT: switch
-; CHECK: ret void
 define void @test22(i32 %arg) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

   call void @foo1()
   ret void
 
 else:
   ret void
-}
+}
 

test/Transforms/SimplifyCFG/switch_create.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 ; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
 
 declare void @foo1()
 
 declare void @foo2()
 
 define void @test1(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1(
-; CHECK:  switch i32 %V, label %F [
-; CHECK:    i32 17, label %T
-; CHECK:    i32 4, label %T
-; CHECK:  ]
 }
 
 define void @test1_ptr(i32* %V) {
-        %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
-        %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; DL-LABEL: @test1_ptr(
+; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
+; DL-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; DL-NEXT:    i32 17, label [[T:%.*]]
+; DL-NEXT:    i32 4, label [[T]]
+; DL-NEXT:    ]
+; DL:       T:
+; DL-NEXT:    call void @foo1()
+; DL-NEXT:    ret void
+; DL:       F:
+; DL-NEXT:    call void @foo2()
+; DL-NEXT:    ret void
+;
+  %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
+  %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr(
-; DL:  %magicptr = ptrtoint i32* %V to i32
-; DL:  switch i32 %magicptr, label %F [
-; DL:    i32 17, label %T
-; DL:    i32 4, label %T
-; DL:  ]
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
-        %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
-        %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; DL-LABEL: @test1_ptr_as1(
+; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16
+; DL-NEXT:    switch i16 [[MAGICPTR]], label [[F:%.*]] [
+; DL-NEXT:    i16 17, label [[T:%.*]]
+; DL-NEXT:    i16 4, label [[T]]
+; DL-NEXT:    ]
+; DL:       T:
+; DL-NEXT:    call void @foo1()
+; DL-NEXT:    ret void
+; DL:       F:
+; DL-NEXT:    call void @foo2()
+; DL-NEXT:    ret void
+;
+  %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
+  %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr_as1(
-; DL:  %magicptr = ptrtoint i32 addrspace(1)* %V to i16
-; DL:  switch i16 %magicptr, label %F [
-; DL:    i16 17, label %T
-; DL:    i16 4, label %T
-; DL:  ]
 }
 
 define void @test2(i32 %V) {
-        %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
-        %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 17, label [[F:%.*]]
+; CHECK-NEXT:    i32 4, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
+  %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test2(
-; CHECK:  switch i32 %V, label %T [
-; CHECK:    i32 17, label %F
-; CHECK:    i32 4, label %F
-; CHECK:  ]
 }
 
 define void @test3(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        br i1 %C1, label %T, label %N
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 4, label [[T:%.*]]
+; CHECK-NEXT:    i32 17, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  br i1 %C1, label %T, label %N
 N:              ; preds = %0
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0
-        call void @foo1( )
-        ret void
 F:              ; preds = %N
-        call void @foo2( )
-        ret void
 
-; CHECK-LABEL: @test3(
-; CHECK: switch i32 %V, label %F [
-; CHECK:     i32 4, label %T
-; CHECK:     i32 17, label %T
-; CHECK:   ]
 }
 
 
 
 define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   %cmp = icmp eq i8 %c, 62
   br i1 %cmp, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry

 lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK-LABEL: @test4(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   switch i8 %c, label %lor.rhs [
-    i8 62, label %lor.end
-    i8 34, label %lor.end
-    i8 92, label %lor.end
   ]
 
 lor.rhs:                                          ; preds = %entry
   %V = icmp eq i8 %c, 92
   br label %lor.end
 
 lor.end:                                          ; preds = %entry, %entry, %entry, %lor.rhs
   %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
-; CHECK-LABEL: @test5(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 
 define i1 @test6({ i32, i32 }* %I) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]]
+; CHECK-NEXT:    [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
 entry:
-        %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
-        %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
-        %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
-        br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
 shortcirc_next.0:               ; preds = %entry
-        %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
-        br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
 shortcirc_next.1:               ; preds = %shortcirc_next.0
-        %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
-        br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
 shortcirc_next.2:               ; preds = %shortcirc_next.1
-        %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
-        br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
 shortcirc_next.3:               ; preds = %shortcirc_next.2
-        %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
-        br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
 shortcirc_next.4:               ; preds = %shortcirc_next.3
-        %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
-        br label %UnifiedReturnBlock
 shortcirc_done.4:               ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
-        br label %UnifiedReturnBlock
 UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
-        %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
-        ret i1 %UnifiedRetVal
 
-; CHECK-LABEL: @test6(
-; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
-; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret void
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99

   ret void
 
 if.end:                                           ; preds = %entry
   ret void
 
-; CHECK-LABEL: @test7(
-; CHECK:   %cmp = icmp ult i32 %x, 32
-; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
+; CHECK:       N:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 0
+;
 entry:
   br i1 %C, label %N, label %if.then
 N:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97

   ret i32 %A
 
 if.end:                                           ; preds = %entry
   ret i32 0
 
-; CHECK-LABEL: @test8(
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
-; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
 ;; This is "Example 7" from http://blog.regehr.org/archives/320
 define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    i8 62, label [[LOR_END]]
+; CHECK-NEXT:    i8 60, label [[LOR_END]]
+; CHECK-NEXT:    i8 59, label [[LOR_END]]
+; CHECK-NEXT:    i8 58, label [[LOR_END]]
+; CHECK-NEXT:    i8 46, label [[LOR_END]]
+; CHECK-NEXT:    i8 44, label [[LOR_END]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 39, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    [[CONV46:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[CONV46]]
+;
 entry:
   %cmp = icmp ult i8 %c, 33
   br i1 %cmp, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry

 lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
   %0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
   %conv46 = zext i1 %0 to i32
   ret i32 %conv46
 
-; CHECK-LABEL: @test9(
-; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
-
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 51, label [[F]]
+; CHECK-NEXT:    i32 0, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       F:
+; CHECK-NEXT:    br label [[T]]
+;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
   %D = and i1 %C, %Cond
   br i1 %D, label %T, label %F
 T:
   ret i32 123
 F:
   ret i32 324
 
-; CHECK-LABEL: @test10(
-; CHECK:  br i1 %Cond, label %switch.early.test, label %F
-; CHECK:switch.early.test:
-; CHECK:  switch i32 %mode, label %T [
-; CHECK:    i32 51, label %F
-; CHECK:    i32 0, label %F
-; CHECK:  ]
 }
 
 ; PR8780
 define i32 @test11(i32 %bar) nounwind {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 55, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 53, label [[RETURN]]
+; CHECK-NEXT:    i32 35, label [[RETURN]]
+; CHECK-NEXT:    i32 24, label [[RETURN]]
+; CHECK-NEXT:    i32 23, label [[RETURN]]
+; CHECK-NEXT:    i32 12, label [[RETURN]]
+; CHECK-NEXT:    i32 4, label [[RETURN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.end:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   %cmp = icmp eq i32 %bar, 4
   %cmp2 = icmp eq i32 %bar, 35
   %or.cond = or i1 %cmp, %cmp2
   %cmp5 = icmp eq i32 %bar, 53

 
 return:                                           ; preds = %if.end, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @test11(
-; CHECK: switch i32 %bar, label %if.end [
-; CHECK:   i32 55, label %return
-; CHECK:   i32 53, label %return
-; CHECK:   i32 35, label %return
-; CHECK:   i32 24, label %return
-; CHECK:   i32 23, label %return
-; CHECK:   i32 12, label %return
-; CHECK:   i32 4, label %return
-; CHECK: ]
 }
 
 define void @test12() nounwind {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK:       bb55.us.us:
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK:       malformed:
+; CHECK-NEXT:    ret void
+;
 entry:
   br label %bb49.us.us
 
 bb49.us.us:
   %A = icmp eq i32 undef, undef

 bb55.us.us:
   br label %bb48.us.us
 
 malformed:
   ret void
-; CHECK-LABEL: @test12(
 
 }
 
 ; test13 - handle switch formation with ult.
 define void @test13(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 2
   br i1 %cmp, label %if.then, label %lor.lhs.false3
 
 lor.lhs.false3:                                   ; preds = %lor.lhs.false

   call void @foo1() noredzone
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test13(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; test14 - handle switch formation with ult.
 define void @test14(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 2, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ugt i32 %x, 2
   br i1 %cmp, label %lor.lhs.false3, label %if.then
 
 lor.lhs.false3:                                   ; preds = %lor.lhs.false

   call void @foo1() noredzone
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test14(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; Don't crash on ginormous ranges.
 define void @test15(i128 %x) nounwind {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:  if.end:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ugt i128 %x, 2
   br i1 %cmp, label %if.end, label %lor.false
 
 lor.false:
   %cmp2 = icmp ne i128 %x, 100000000000000000000

   br label %if.end
 
 if.end:
   ret void
 
-; CHECK-LABEL: @test15(
-; CHECK-NOT: switch
-; CHECK: ret void
 }
 
 ; PR8675
 ; rdar://5134905
 define zeroext i1 @test16(i32 %x) nounwind {
-entry:
 ; CHECK-LABEL: @test16(
-; CHECK: %x.off = add i32 %x, -1
-; CHECK: %switch = icmp ult i32 %x.off, 3
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
+entry:
   %cmp.i = icmp eq i32 %x, 1
   br i1 %cmp.i, label %lor.end, label %lor.lhs.false
 
 lor.lhs.false:
   %cmp.i2 = icmp eq i32 %x, 2

   ret i1 %0
 }
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
+; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK:       lor.lhs.false8:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
   br i1 %or.cond775, label %lor.lhs.false8, label %return
 

   ret void
 
 return:
   ret void
 
-; CHECK-LABEL: @test17(
-; CHECK-NOT: switch.early.test
-; CHECK-NOT: switch i32
-; CHECK: ret void
 }
 
 define void @test18(i32 %arg) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]]
+; CHECK:       bb19:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    br label [[BB20]]
+; CHECK:       bb20:
+; CHECK-NEXT:    ret void
+;
 bb:
   %tmp = and i32 %arg, -2
   %tmp1 = icmp eq i32 %tmp, 8
   %tmp2 = icmp eq i32 %arg, 10
   %tmp3 = or i1 %tmp1, %tmp2

   br label %bb20
 
 bb20:                                             ; preds = %bb19, %bb8
   ret void
 
-; CHECK-LABEL: @test18(
-; CHECK: %arg.off = add i32 %arg, -8
-; CHECK: icmp ult i32 %arg.off, 11
 }
 
 define void @PR26323(i1 %tobool23, i32 %tmp3) {
+; CHECK-LABEL: @PR26323(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0
+; CHECK-NEXT:    [[NEG14:%.*]] = and i32 [[TMP3]], -2
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]]
+; CHECK-NEXT:    [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]]
+; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]]
+; CHECK:       if.then27:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    unreachable
+; CHECK:       if.end29:
+; CHECK-NEXT:    ret void
+;
 entry:
   %tobool5 = icmp ne i32 %tmp3, 0
   %neg14 = and i32 %tmp3, -2
   %cmp17 = icmp ne i32 %neg14, -1
   %or.cond = and i1 %tobool5, %tobool23

 
 if.end29:                                         ; preds = %entry
   ret void
 }
 
-; CHECK-LABEL: define void @PR26323(
-; CHECK:  %tobool5 = icmp ne i32 %tmp3, 0
-; CHECK:  %neg14 = and i32 %tmp3, -2
-; CHECK:  %cmp17 = icmp ne i32 %neg14, -1
-; CHECK:  %or.cond = and i1 %tobool5, %tobool23
-; CHECK:  %or.cond1 = and i1 %cmp17, %or.cond
-; CHECK:  br i1 %or.cond1, label %if.end29, label %if.then27
-
 ; Form a switch when and'ing a negated power of two
-; CHECK-LABEL: define void @test19
-; CHECK: switch i32 %arg, label %else [
-; CHECK: i32 32, label %if
-; CHECK: i32 13, label %if
-; CHECK: i32 12, label %if
 define void @test19(i32 %arg) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    i32 32, label [[IF:%.*]]
+; CHECK-NEXT:    i32 13, label [[IF]]
+; CHECK-NEXT:    i32 12, label [[IF]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
-; CHECK-LABEL: define void @test20
-; CHECK-NOT: switch
-; CHECK: ret void
 define void @test20(i32 %arg) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Form a switch when or'ing a power of two
-; CHECK-LABEL: define void @test21
-; CHECK: i32 32, label %else
-; CHECK: i32 13, label %else
-; CHECK: i32 12, label %else
 define void @test21(i32 %arg) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
+; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
+; CHECK-NEXT:    i32 13, label [[ELSE]]
+; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
-; CHECK-LABEL: define void @test22
-; CHECK-NOT: switch
-; CHECK: ret void
 define void @test22(i32 %arg) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else

   call void @foo1()
   ret void
 
 else:
   ret void
-}
+}