ARM: add support for QBIT

[compnerd]

Summary

Add support for the __ARM_FEATURE_QBIT preprocessor macro. Also add associated
intrinsics for checking the state of the Q flag. This is supported on ARMv5
variant 'e' and later CPUs. These implement section 6.4.6 and 9.1.1 of the
ACLE.

[kongyi]

Hi Saleem,

The patch is missing unit tests for the ACLE header.

Thanks,
Yi

lib/Headers/arm_acle.h

110

According to ACLE 2.0:

... intrinsics are available when __ARM_FEATURE_QBIT is defined

Please guard these functions with the corresponding flag.

[t.p.northover]

Hi Saleem,

I don't think these are quite right yet...

lib/Headers/arm_acle.h

116

I think ACLE says this function should return 1 when the flag is set.

121

This also doesn't seem to do what ACLE says: set the Q flag based on the LSB of the input.

Also, I don't think "cpsr_q" exists, does it? Both the v7A and v7M descriptions I've found lump it in with NZCV (i.e. "cpsr_nzcvq"). Which probably means the assembly should be marked as clobbering CPSR too.

[t.p.northover]

I'm also a bit worried about how these intrinsics will work on v5 cores. Perhaps __ARM_FEATURE_QBIT should only be defined in ARM mode there?

Cheers.

Tim.

[rengolin]

lib/Headers/arm_acle.h

121

I may be wrong, but I think you need to mrs first to get the bit pattern, change this value based on (occurred != 0) shifted to the right place and writing it back with msr, or you'll end up writing zeroes to the other flags. Or is that only the case with registers?

125

This will probably need some builtin/intrinsic, since, if I read the ACLE correctly, the context is from *here* to the end of the scope. But it can be left for another set of patches, obviously.

[t.p.northover]

lib/Headers/arm_acle.h

121

That would preserve NZCV and allow LLVM more optimisation freedom, but at the cost of a more expensive __set_saturation_occurred.

As long as LLVM's aware that we *have* clobbered NZCV (slightly confusingly tracked as CPSR in the 32-bit backend) it should work either way.

Of course, we don't actually model Q now, so we're not making the required guarantees anyway (I think LLVM would consider itself free to move a QADD past these no matter what we do, for example).

[rengolin]

lib/Headers/arm_acle.h

121

Shouldn't we be fixing that in LLVM first, then?

lib/Basic/Targets.cpp

     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
   }
+  bool hasQFlag(StringRef ArchName, unsigned CPUArchVer) const {
+    // ARMv5 variant 'e' and later have bit[27] of the CPSR defined as the Q bit
+    return CPUArchVer > 5 || ArchName.endswith("v5e") ||
+           ArchName.endswith("v5te");
+  }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     // Target identification.

 
     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
 
+    // ACLE 6.4.6 Q (saturation) flag
+    if (hasQFlag(ArchName, CPUArchVer))
+      Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
+
     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
     if (!CPUProfile.empty())
       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");

lib/Headers/arm_acle.h

 }
 
 /* 9 DATA-PROCESSING INTRINSICS */
+
+/* 9.1.1 The Q (saturation) flag */
+static __inline__ int __attribute__((always_inline, nodebug))
+__saturation_occurred(void) {
+  uint32_t cpsr;
+  __asm__ __volatile__("mrs %0, cpsr" : "=r"(cpsr));
+  return cpsr & 0x08000000;
+}
+
+static __inline__ void __attribute__((always_inline, nodebug))
+__set_saturation_occurred(int occurred) {
+  __asm__ __volatile__ ("msr cpsr_q, %0" : : "r" (occurred));
+}
+
+static __inline__ void __attribute__((always_inline, nodebug))
+__ignore_saturation(void) {
+  /* not yet implemented */
+}
+
 /* 9.2 Miscellaneous data-processing intrinsics */
 /* ROR */
 static __inline__ uint32_t __attribute__((always_inline, nodebug))

test/Preprocessor/arm-acle-6.4.c

 // CHECK-CORTEX-M0-NOT: __ARM_ARCH_ISA_ARM
 // CHECK-CORTEX-M0: __ARM_ARCH_ISA_THUMB 1
 // CHECK-CORTEX-M0: __ARM_ARCH_PROFILE 'M'
+// CHECK-CORTEX-M0: __ARM_FEATURE_QBIT 1
 // CHECK-CORTEX-M0-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
 // CHECK-CORTEX-M0-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
 

 // CHECK-ARM810: __ARM_ARCH_ISA_ARM 1
 // CHECK-ARM810-NOT: __ARM_ARCH_ISA_THUMB
 // CHECK-ARM810-NOT: __ARM_ARCH_PROFILE
+// CHECK-ARM810-NOT: __ARM_FEATURE_QBIT
 // CHECK-ARM810-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
 // CHECK-ARM810-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
 

 // CHECK-ARM7TDMI: __ARM_ARCH_ISA_ARM 1
 // CHECK-ARM7TDMI: __ARM_ARCH_ISA_THUMB 1
 // CHECK-ARM7TDMI-NOT: __ARM_ARCH_PROFILE
+// CHECK-ARM7TDMI-NOT: __ARM_FEATURE_QBIT
 
 // RUN: %clang -target arm-eabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-A7
 

 // CHECK-CORTEX-A7: __ARM_ARCH_ISA_ARM 1
 // CHECK-CORTEX-A7: __ARM_ARCH_ISA_THUMB 2
 // CHECK-CORTEX-A7: __ARM_ARCH_PROFILE 'A'
+// CHECK-CORTEX-A7: __ARM_FEATURE_QBIT
 // CHECK-CORTEX-A7-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
 // CHECK-CORTEX-A7-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
 

 // CHECK-CORTEX-R4: __ARM_ARCH_ISA_ARM 1
 // CHECK-CORTEX-R4: __ARM_ARCH_ISA_THUMB 2
 // CHECK-CORTEX-R4: __ARM_ARCH_PROFILE 'R'
+// CHECK-CORTEX-R4: __ARM_FEATURE_QBIT
+
+// RUN: %clang -target arm-eabi -mcpu=arm10tdmi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARMv5
+
+// CHECK-ARMv5-NOT: __ARM_FEATURE_QBIT
+
+// RUN: %clang -target arm-eabi -mcpu=arm10e -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARMv5TE
+
+// CHECK-ARMv5TE: __ARM_FEATURE_QBIT