This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are significantly improved generally.
Instructions / Tablegen:
- The ...AndK instruction classes are modified to select the K instruction instead of the 2-address equivalent one.
- The isConvertibleToThreeAddress flags on the 2-address instructions have been removed, since it did not seem to have any use (not sure if it should actually be kept for any future possible use?).
- The getThreeOperandOpcode instruction mapping has been replaced by the inverse getTwoOperandOpcode mapping. This is wrapped by SystemZInstrInfo::get2AddrOpcode() so that it can be accessed outside of SystemZInstrInfo.cpp. The generated function returns -1 if there is no mapped instruction, and this is I hope future-safe to use like done now.
convertToThreeAddress()
- Code that used getThreeOperandOpcode() removed.
- finishConvertToThreeAddress() inlined.
- The And -> RISBG conversions are not yet modified. Would this be worth handling as well (it seems the instructions are of the same cost)?
RegAlloc
- Hinting the potentially tied register, which helps a bit.
SystemZShortenInst
- Handling added to convert to 2-address instruction when possible.
Opcode counts Impact (truncated after topmost 20 opcodes):
master <> "*only* changing isel to select 3-address"
agrk : 7117 42856 +35739 ahi : 34952 485 -34467 ahik : 26316 59979 +33663 agr : 33596 0 -33596 ark : 4972 24636 +19664 ar : 18918 0 -18918 aghik : 4980 23689 +18709 sgrk : 9026 27288 +18262 sgr : 18059 0 -18059 sll : 15965 241 -15724 sllk : 4607 20324 +15717 aghi : 37856 28011 -9845 jne : 13952 22838 +8886 brctg : 8727 124 -8603 srk : 3719 9855 +6136 sr : 6008 0 -6008 lgr : 354991 350453 -4538 srl : 4318 44 -4274 srlk : 3097 7366 +4269 Spill|Reload : 188117 186340 -1777
"isel 3-address" <> "isel 3-address + handling to shorten instructions whenever possible"
ahik : 59979 31669 -28310 ahi : 485 27587 +27102 aghik : 23689 7215 -16474 sllk : 20324 6717 -13607 sll : 241 13848 +13607 agrk : 42856 32331 -10525 agr : 0 10525 +10525 sgr : 0 9643 +9643 sgrk : 27288 17645 -9643 ar : 0 9182 +9182 ark : 24636 15454 -9182 jne : 22838 13985 -8853 brctg : 124 8715 +8591 aghi : 28011 35894 +7883 srk : 9855 5566 -4289 sr : 0 4289 +4289 srl : 44 3475 +3431 srlk : 7366 3935 -3431 ngr : 668 2662 +1994
"isel 3-address + shortening" <> "isel 3-address + shortening + regalloc hints"
sgr : 9643 12424 +2781 sgrk : 17645 14864 -2781 agrk : 32331 30205 -2126 agr : 10525 12648 +2123 ahi : 27587 28435 +848 ahik : 31669 30826 -843 aghik : 7215 6550 -665 sr : 4289 4825 +536 srk : 5566 5032 -534 ar : 9182 9695 +513 ark : 15454 14945 -509 aghi : 35894 36359 +465 sll : 13848 14079 +231 sllk : 6717 6490 -227 srak : 1407 1199 -208 sra : 1943 2151 +208 srl : 3475 3652 +177 srlk : 3935 3760 -175 lgr : 350453 350599 +146 Spill|Reload : 186340 186303 -37
Not sure exactly why, but the BRCTX conversions really suffered for just doing three-address, but this problem seems to disappear with shortening in place.