[GlobalISel][AArch64] Legalize/select G_(S/Z/ANY)_EXT for v8s8s

[paquette]

Summary

This adds legalization for G_SEXT, G_ZEXT, and G_ANYEXT for v8s8s.

We were falling back on G_ZEXT in arm64-vabs.ll before, preventing us from selecting the @llvm.aarch64.neon.sabd.v8i8 intrinsic.

This adds legalizer support for those 3, which gives us selection via the importer. Update the relevant tests (legalize-ext.mir, select-int-ext.mir) and add a GISel line to arm64-vabs.ll.

[paquette]

Just realized that the G_ZEXT is the only thing relevant to check for in arm64-vabs.ll. Remove unnecessary check lines.

llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   getActionDefinitionsBuilder(G_FCMP)
       .legalFor({{s32, s32}, {s32, s64}})
       .clampScalar(0, s32, s32)
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(1);
 
   // Extensions
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
-      .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
+      .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
+      .legalFor({v8s16, v8s8});
 
   getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
 
   // FP conversions
   getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
       {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});
   getActionDefinitionsBuilder(G_FPEXT).legalFor(
       {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}});

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir

bb.0:
     ; CHECK: $w0 = COPY [[AND]](s32)
     %0:_(s32) = COPY $w0
     %1:_(s1) = G_TRUNC %0(s32)
     %2:_(s8) = G_ZEXT %1(s1)
     %3:_(s32) = G_ANYEXT %2(s8)
     $w0 = COPY %3(s32)
 
 ...
+---
+name:            test_zext_v8s16_from_v8s8
+alignment:       2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: test_zext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+    ; CHECK: $q0 = COPY [[ZEXT]](<8 x s16>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %1:fpr(<8 x s8>) = COPY $d0
+    %2:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+...
+---
+name:            test_sext_v8s16_from_v8s8
+alignment:       2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: test_sext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+    ; CHECK: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+    ; CHECK: $q0 = COPY [[SEXT]](<8 x s16>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %1:fpr(<8 x s8>) = COPY $d0
+    %2:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+...
+---
+name:            test_anyext_v8s16_from_v8s8
+alignment:       2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: test_anyext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
+    ; CHECK: $q0 = COPY [[ANYEXT]](<8 x s16>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %1:fpr(<8 x s8>) = COPY $d0
+    %2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @anyext_s64_from_s32() { ret void }
   define void @anyext_s32_from_s8() { ret void }
+  define void @anyext_v8s16_from_v8s8() { ret void }
 
   define void @zext_s64_from_s32() { ret void }
   define void @zext_s32_from_s16() { ret void }
   define void @zext_s32_from_s8() { ret void }
   define void @zext_s16_from_s8() { ret void }
+  define void @zext_v8s16_from_v8s8() { ret void }
 
   define void @sext_s64_from_s32() { ret void }
   define void @sext_s32_from_s16() { ret void }
   define void @sext_s32_from_s8() { ret void }
   define void @sext_s16_from_s8() { ret void }
+  define void @sext_v8s16_from_v8s8() { ret void }
 ...
 
 ---
 name:            anyext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 registers:
bb.0:
     ; CHECK: $w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY $w0
     %0(s8) = G_TRUNC %2
     %1(s32) = G_ANYEXT %0
     $w0 = COPY %1(s32)
 ...
 
 ---
+name:            anyext_v8s16_from_v8s8
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: anyext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+    ; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
+    $q0 = COPY %1(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+---
 name:            zext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
bb.0:
     %2:gpr(s32) = COPY $w0
     %0(s8) = G_TRUNC %2
     %1(s16) = G_ZEXT %0
     %3:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %3(s32)
 ...
 
 ---
+name:            zext_v8s16_from_v8s8
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: zext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+    ; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+    $q0 = COPY %1(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+...
+
+---
 name:            sext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
bb.0:
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
     ; CHECK: $w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY $w0
     %0(s8) = G_TRUNC %2
     %1(s16) = G_SEXT %0
     %3:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %3(s32)
 ...
+
+---
+name:            sext_v8s16_from_v8s8
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: sext_v8s16_from_v8s8
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
+    ; CHECK: $q0 = COPY [[SSHLLv8i8_shift]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(<8 x s8>) = COPY $d0
+    %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
+    $q0 = COPY %1(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+...

llvm/test/CodeGen/AArch64/arm64-vabs.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
 
-
+; FALLBACK-NOT: remark:{{.*}}(<8 x s16>) = G_ZEXT %4:_(<8 x s8>)
+; FALLBACK-NOT: remark:{{.*}} sabdl8h
 define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabdl8h:
 ;CHECK: sabdl.8h
+;GISEL-LABEL: sabdl8h:
+;GISEL: sabdl.8h
         %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
         ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {