Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateADDRegShift

[teemperor]

Summary

As reported in LLVM bug 41487, the check in this function is wrong and should be
the same as the described check in the comment (which is correctly copied from the
ARM ISA reference).

[davide]

Add an unittest maybe? otherwise, seems to match the ISA so LGTM

[teemperor]

I don't think I can provide a test for this because I don't really know the code so well (and generating an UNPREDICTABLE seems tricky too). I'll leave this up for a bit to see if someone comes up with a test (or I'll have time to dig into the code) and then commit.

lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

case eEncodingA1:
       m = Bits32(opcode, 3, 0);
       s = Bits32(opcode, 11, 8);
 
       // setflags = (S == '1'); shift_t = DecodeRegShift(type);
       setflags = BitIsSet(opcode, 20);
       shift_t = DecodeRegShift(Bits32(opcode, 6, 5));
 
       // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
-      if ((d == 15) || (m == 15) || (m == 15) || (s == 15))
+      if ((d == 15) || (n == 15) || (m == 15) || (s == 15))
         return false;
       break;
 
     default:
       return false;
     }
 
     // shift_n = UInt(R[s]<7:0>);