[X86] Make the post machine scheduler macrofusion-aware.

[courbet]

Summary

Given that X86 does not use this currently, this is an NFC. I'll
experiment with enabling and will report numbers.

[andreadb]

Sounds reasonable to me.

I look forward to seeing the results from your experiment.

[courbet]

Thanks Andrea.

[lebedev.ri]

Given that X86 does not use this currently, this is an NFC.

Are you sure?

In D59688#1446261, @courbet wrote:

In D59688#1446250, @lebedev.ri wrote:

In D59688#1446142, @courbet wrote:

This could use test coverage i guess?

This is actually an NFC as the post-ra scheduler is not on by default. The next patch that enables scheduling will show the actual changes.

What about CPU's that specify let PostRAScheduler = 1; ?

Ah yes, sorry I lost track of this. Interestingly there are no tests that fail currently. I'll try to come up with some that do.

For now I'll submit the refactoring part of this change (D59689).

[courbet]

Are you sure ?

To enable this you need either the flag, or substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); in your target. Only Arm, Aaarch64, PPC and SytemZ add the pass manually.

llvm/lib/Target/X86/X86TargetMachine.cpp

public:
 
   ScheduleDAGInstrs *
   createMachineScheduler(MachineSchedContext *C) const override {
     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
     DAG->addMutation(createX86MacroFusionDAGMutation());
     return DAG;
   }
 
+  ScheduleDAGInstrs *
+  createPostMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
+    DAG->addMutation(createX86MacroFusionDAGMutation());
+    return DAG;
+  }
+
   void addIRPasses() override;
   bool addInstSelector() override;
   bool addIRTranslator() override;
   bool addLegalizeMachineIR() override;
   bool addRegBankSelect() override;
   bool addGlobalInstructionSelect() override;
   bool addILPOpts() override;
   bool addPreISel() override;

llvm/test/CodeGen/X86/testb-je-fusion.ll

 ; NOFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  .LBB0_2: # %if.end
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    retq
 ;
 ; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_test_je:
 ; BRANCHFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    xorl %eax, %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    testl $512, %edi # imm = 0x200
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    testl $512, %edi # imm = 0x200
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    je .LBB0_2
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  .LBB0_2: # %if.end
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    retq
 entry:
   %and = and i32 %flags, 512
   %tobool = icmp eq i32 %and, 0

 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    retq
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  .LBB1_1:
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    xorl %eax, %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    retq
 ;
 ; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_cmp_je:
 ; BRANCHFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    cmpl $512, %edi # imm = 0x200
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    cmpl $512, %edi # imm = 0x200
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    je .LBB1_1
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  # %bb.2: # %if.then
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    retq
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  .LBB1_1:
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    xorl %eax, %eax
 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    retq
 entry:

 ; NOFUSION_MISCHEDPOSTRA-NEXT:    addl $-512, %eax # imm = 0xFE00
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    je .LBB2_2
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  .LBB2_2: # %if.end
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    retq
 ;
-; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
-; BRANCHFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    addl $-512, %eax # imm = 0xFE00
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    je .LBB2_2
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  .LBB2_2: # %if.end
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    retq
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
+; BRANCHFUSIONONLY_MISCHEDPOSTRA:       # %bb.0: # %entry
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    addl $-512, %eax # imm = 0xFE00
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    je .LBB2_2
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movl $1, %eax
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:  .LBB2_2: # %if.end
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    retq
+;
+; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
+; MACROFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    addl $-512, %eax # imm = 0xFE00
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    je .LBB2_2
+; MACROFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
+; MACROFUSION_MISCHEDPOSTRA-NEXT:  .LBB2_2: # %if.end
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    retq
 entry:
   %sub = sub i32 %flags, 512
   %tobool = icmp eq i32 %sub, 0
   store i8 1, i8* %p
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   br label %if.end

 ; NOFUSION_MISCHEDPOSTRA-NEXT:    decl %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    je .LBB3_2
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
 ; NOFUSION_MISCHEDPOSTRA-NEXT:  .LBB3_2: # %if.end
 ; NOFUSION_MISCHEDPOSTRA-NEXT:    retq
 ;
-; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
-; BRANCHFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    decl %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    je .LBB3_2
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:  .LBB3_2: # %if.end
-; BRANCHFUSION_MISCHEDPOSTRA-NEXT:    retq
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
+; BRANCHFUSIONONLY_MISCHEDPOSTRA:       # %bb.0: # %entry
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    decl %eax
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    je .LBB3_2
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    movl $1, %eax
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:  .LBB3_2: # %if.end
+; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT:    retq
+;
+; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
+; MACROFUSION_MISCHEDPOSTRA:       # %bb.0: # %entry
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movl %edi, %eax
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movb $1, (%rsi)
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    decl %eax
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    je .LBB3_2
+; MACROFUSION_MISCHEDPOSTRA-NEXT:  # %bb.1: # %if.then
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    movl $1, %eax
+; MACROFUSION_MISCHEDPOSTRA-NEXT:  .LBB3_2: # %if.end
+; MACROFUSION_MISCHEDPOSTRA-NEXT:    retq
 entry:
   %sub = sub i32 %flags, 1
   %tobool = icmp eq i32 %sub, 0
   store i8 1, i8* %p
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   br label %if.end
 
 if.end:
   %hasflag = phi i32 [ 1, %if.then ], [ %sub, %entry ]
   ret i32 %hasflag
 }