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Differential D60185

[X86] Make the post machine scheduler macrofusion-aware.
ClosedPublic

Authored by courbet on Apr 3 2019, 1:42 AM.

Details

Reviewers
andreadb
lebedev.ri
Commits
rG26a8ed3ac98a: [X86] Make the post machine scheduler macrofusion-aware.
rL357568: [X86] Make the post machine scheduler macrofusion-aware.
Summary

Given that X86 does not use this currently, this is an NFC. I'll
experiment with enabling and will report numbers.

Diff Detail

Repository
rL LLVM

Event Timeline

courbet created this revision.Apr 3 2019, 1:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 3 2019, 1:42 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
Harbormaster completed remote builds in B29994: Diff 193445.Apr 3 2019, 1:42 AM
andreadb accepted this revision.Apr 3 2019, 2:32 AM

Sounds reasonable to me.

I look forward to seeing the results from your experiment.

This revision is now accepted and ready to land.Apr 3 2019, 2:32 AM
courbet added a comment.Apr 3 2019, 2:35 AM

Thanks Andrea.

Closed by commit rL357568: [X86] Make the post machine scheduler macrofusion-aware. (authored by courbet). · Explain WhyApr 3 2019, 2:37 AM
This revision was automatically updated to reflect the committed changes.
lebedev.ri added a comment.Apr 3 2019, 3:08 AM

Given that X86 does not use this currently, this is an NFC.

Are you sure?

In D59688#1446261, @courbet wrote:
In D59688#1446250, @lebedev.ri wrote:
In D59688#1446142, @courbet wrote:

This could use test coverage i guess?

This is actually an NFC as the post-ra scheduler is not on by default. The next patch that enables scheduling will show the actual changes.

What about CPU's that specify let PostRAScheduler = 1; ?

Ah yes, sorry I lost track of this. Interestingly there are no tests that fail currently. I'll try to come up with some that do.

For now I'll submit the refactoring part of this change (D59689).

courbet added a comment.Apr 3 2019, 4:14 AM

Are you sure ?

To enable this you need either the flag, or substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); in your target. Only Arm, Aaarch64, PPC and SytemZ add the pass manually.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
7 lines
test/
CodeGen/
X86/
66 lines

Diff 193456

llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Linespublic:
ScheduleDAGInstrs * ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const override { createMachineScheduler(MachineSchedContext *C) const override {
ScheduleDAGMILive *DAG = createGenericSchedLive(C); ScheduleDAGMILive *DAG = createGenericSchedLive(C);
DAG->addMutation(createX86MacroFusionDAGMutation()); DAG->addMutation(createX86MacroFusionDAGMutation());
return DAG; return DAG;
} }
ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext *C) const override {
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
DAG->addMutation(createX86MacroFusionDAGMutation());
return DAG;
}
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addIRTranslator() override; bool addIRTranslator() override;
bool addLegalizeMachineIR() override; bool addLegalizeMachineIR() override;
bool addRegBankSelect() override; bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override;
bool addILPOpts() override; bool addILPOpts() override;
bool addPreISel() override; bool addPreISel() override;
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/testb-je-fusion.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_test_je: ; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_test_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: testl $512, %edi # imm = 0x200
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: testl $512, %edi # imm = 0x200
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB0_2 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB0_2
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq
entry: entry:
%and = and i32 %flags, 512 %and = and i32 %flags, 512
%tobool = icmp eq i32 %and, 0 %tobool = icmp eq i32 %and, 0
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1: ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1:
; NOFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_cmp_je: ; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_cmp_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB1_1 ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB1_1
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.2: # %if.then ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.2: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1: ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1:
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq
entry: entry:
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; NOFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00 ; NOFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2 ; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2
; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je: ; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00 ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2 ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB2_2
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; MACROFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; MACROFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2
; MACROFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; MACROFUSION_MISCHEDPOSTRA-NEXT: retq
entry: entry:
%sub = sub i32 %flags, 512 %sub = sub i32 %flags, 512
%tobool = icmp eq i32 %sub, 0 %tobool = icmp eq i32 %sub, 0
store i8 1, i8* %p store i8 1, i8* %p
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
if.then: if.then:
br label %if.end br label %if.end
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; NOFUSION_MISCHEDPOSTRA-NEXT: decl %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2 ; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2
; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je: ; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: decl %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: decl %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2 ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB3_2
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; MACROFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2
; MACROFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; MACROFUSION_MISCHEDPOSTRA-NEXT: retq
entry: entry:
%sub = sub i32 %flags, 1 %sub = sub i32 %flags, 1
%tobool = icmp eq i32 %sub, 0 %tobool = icmp eq i32 %sub, 0
store i8 1, i8* %p store i8 1, i8* %p
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
if.then: if.then:
br label %if.end br label %if.end
if.end: if.end:
%hasflag = phi i32 [ 1, %if.then ], [ %sub, %entry ] %hasflag = phi i32 [ 1, %if.then ], [ %sub, %entry ]
ret i32 %hasflag ret i32 %hasflag
} }