[llvm-exegesis] Handle CMOV's OPERAND_COND_CODE OperandType

[lebedev.ri]

Summary

D60041 will regress/break CMOV benchmarking.

This at least allows to not crash on the opcode.
However, this still won't generate all the snippets with all the condcode enumerators.

[courbet]

Thanks Roman. I only have a comment regarding documentation.

tools/llvm-exegesis/lib/Target.h

105 ↗

(On Diff #193054)

This would need some documentation, e.g.

// Assigns a random operand of the right type to variable Var. The default implementation only handles generic operand types. The target is responsible for handling any operand starting from OPERAND_FIRST_TARGET.

[lebedev.ri]

tools/llvm-exegesis/lib/SnippetGenerator.cpp

49 ↗

(On Diff #193054)

Any advice on how to best produce multiple variants covering all the condcodes?
The obvious solution could be to pass BenchmarkCode to Target hook that would
duplicate it for each of the possible condcodes,
and return vector that would get appended to Output.
Is that on the right track? Anything cleaner?

[lebedev.ri]

Add comment.

[courbet]

tools/llvm-exegesis/lib/SnippetGenerator.cpp

49 ↗

(On Diff #193054)

I think the original idea was to generate several identical templates and let randomization handle exploration. With what you just implemented when generating several instances of the same template you always get the same cond code because you wrote:

AssignedValue = llvm::MCOperand::createImm(1);

if you did something like:

AssignedValue = llvm::MCOperand::createImm(random_int_in_range(0, 2));

Then half of your generated snippets would go each way.

+ @gchatelet who started[[ https://github.com/llvm-mirror/llvm/commit/b1497a74adb1d3669dbb16a9e02ee5214ea211a6 | implementing support for exploration ]].

[lebedev.ri]

tools/llvm-exegesis/lib/SnippetGenerator.cpp

49 ↗

(On Diff #193054)

Hmm, yes, that is the least intrusive solution, but that is waay too brittle. :(
Is that really the recommended solution here, given that we know all the affected opcodes and the possible condcodes?

[gchatelet]

tools/llvm-exegesis/lib/SnippetGenerator.cpp

49 ↗

(On Diff #193054)

Thx for the fix @lebedev.ri
I'm not sure to understand what you mean by waay too brittle. Keep in mind that we want to explore as much as possible and - for sure - we can be more efficient when we know the semantic of a dimension but we also want to discover new behavior that were not known before.
There's a tension between the two obviously. For now I would just stick to this Patch. I'll work on value exploration as soon as possible - I'm especially interested in floating point values.

[lebedev.ri]

Now that the parent patches has landed, will try to rebase and land tomorrow.

llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s

+# RUN: llvm-exegesis -mode=latency -opcode-name=CMOV32rr | FileCheck %s
+
+CHECK:      ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT:   instructions:
+CHECK-NEXT:     CMOV32rr
+CHECK-NEXT: config: ''
+CHECK-LAST: ...

llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h

 
 // Picks a random configuration, then selects a random def and a random use from
 // it and finally set the selected values in the provided InstructionInstances.
 void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
                        InstructionTemplate &DefIB, InstructionTemplate &UseIB);
 
 // Assigns a Random Value to all Variables in IT that are still Invalid.
 // Do not use any of the registers in `ForbiddenRegs`.
-void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
+void randomizeUnsetVariables(const ExegesisTarget &Target,
+                             const llvm::BitVector &ForbiddenRegs,
                              InstructionTemplate &IT);
 
 } // namespace exegesis
 } // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_SNIPPETGENERATOR_H

llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp

 //===-- SnippetGenerator.cpp ------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include <array>
 #include <string>
 
 #include "Assembler.h"
 #include "MCInstrDescView.h"
 #include "SnippetGenerator.h"
+#include "Target.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/Program.h"
 
 namespace llvm {
for (CodeTemplate &CT : E.get()) {
           CT.ScratchSpacePointerInReg
               ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
               : RATC.emptyRegisters();
       // TODO: Generate as many BenchmarkCode as needed.
       {
         BenchmarkCode BC;
         BC.Info = CT.Info;
         for (InstructionTemplate &IT : CT.Instructions) {
-          randomizeUnsetVariables(ForbiddenRegs, IT);
+          randomizeUnsetVariables(State.getExegesisTarget(), ForbiddenRegs, IT);
           BC.Instructions.push_back(IT.build());
         }
         if (CT.ScratchSpacePointerInReg)
           BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
         BC.RegisterInitialValues =
             computeRegisterInitialValues(CT.Instructions);
         Output.push_back(std::move(BC));
       }
static size_t randomIndex(size_t Size) {
   return Distribution(randomGenerator());
 }
 
 template <typename C>
 static auto randomElement(const C &Container) -> decltype(Container[0]) {
   return Container[randomIndex(Container.size())];
 }
 
-static void randomize(const Instruction &Instr, const Variable &Var,
-                      llvm::MCOperand &AssignedValue,
-                      const llvm::BitVector &ForbiddenRegs) {
-  const Operand &Op = Instr.getPrimaryOperand(Var);
-  switch (Op.getExplicitOperandInfo().OperandType) {
-  case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
-    // FIXME: explore immediate values too.
-    AssignedValue = llvm::MCOperand::createImm(1);
-    break;
-  case llvm::MCOI::OperandType::OPERAND_REGISTER: {
-    assert(Op.isReg());
-    auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
-    assert(AllowedRegs.size() == ForbiddenRegs.size());
-    for (auto I : ForbiddenRegs.set_bits())
-      AllowedRegs.reset(I);
-    AssignedValue = llvm::MCOperand::createReg(randomBit(AllowedRegs));
-    break;
-  }
-  default:
-    break;
-  }
-}
-
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
                                     InstructionTemplate &IB) {
   assert(ROV.Op);
   if (ROV.Op->isExplicit()) {
     auto &AssignedValue = IB.getValueFor(*ROV.Op);
     if (AssignedValue.isValid()) {
       assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
       return;
void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
                        InstructionTemplate &DefIB, InstructionTemplate &UseIB) {
   assert(!AliasingConfigurations.empty());
   assert(!AliasingConfigurations.hasImplicitAliasing());
   const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
   setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
   setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
-void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
+void randomizeUnsetVariables(const ExegesisTarget &Target,
+                             const llvm::BitVector &ForbiddenRegs,
                              InstructionTemplate &IT) {
   for (const Variable &Var : IT.Instr.Variables) {
     llvm::MCOperand &AssignedValue = IT.getValueFor(Var);
     if (!AssignedValue.isValid())
-      randomize(IT.Instr, Var, AssignedValue, ForbiddenRegs);
+      Target.randomizeMCOperand(IT.Instr, Var, AssignedValue, ForbiddenRegs);
   }
 }
 
 } // namespace exegesis
 } // namespace llvm

llvm/trunk/tools/llvm-exegesis/lib/Target.h

public:
 
   // Returns the maximum number of bytes a load/store instruction can access at
   // once. This is typically the size of the largest register available on the
   // processor. Note that this only used as a hint to generate independant
   // load/stores to/from memory, so the exact returned value does not really
   // matter as long as it's large enough.
   virtual unsigned getMaxMemoryAccessSize() const { return 0; }
 
+  // Assigns a random operand of the right type to variable Var.
+  // The default implementation only handles generic operand types.
+  // The target is responsible for handling any operand
+  // starting from OPERAND_FIRST_TARGET.
+  virtual void randomizeMCOperand(const Instruction &Instr, const Variable &Var,
+                                  llvm::MCOperand &AssignedValue,
+                                  const llvm::BitVector &ForbiddenRegs) const;
+
   // Creates a snippet generator for the given mode.
   std::unique_ptr<SnippetGenerator>
   createSnippetGenerator(InstructionBenchmark::ModeE Mode,
                          const LLVMState &State) const;
   // Creates a benchmark runner for the given mode.
   std::unique_ptr<BenchmarkRunner>
   createBenchmarkRunner(InstructionBenchmark::ModeE Mode,
                         const LLVMState &State) const;

llvm/trunk/tools/llvm-exegesis/lib/Target.cpp

std::unique_ptr<BenchmarkRunner> ExegesisTarget::createLatencyBenchmarkRunner(
   return llvm::make_unique<LatencyBenchmarkRunner>(State, Mode);
 }
 
 std::unique_ptr<BenchmarkRunner>
 ExegesisTarget::createUopsBenchmarkRunner(const LLVMState &State) const {
   return llvm::make_unique<UopsBenchmarkRunner>(State);
 }
 
+void ExegesisTarget::randomizeMCOperand(
+    const Instruction &Instr, const Variable &Var,
+    llvm::MCOperand &AssignedValue,
+    const llvm::BitVector &ForbiddenRegs) const {
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  switch (Op.getExplicitOperandInfo().OperandType) {
+  case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
+    // FIXME: explore immediate values too.
+    AssignedValue = llvm::MCOperand::createImm(1);
+    break;
+  case llvm::MCOI::OperandType::OPERAND_REGISTER: {
+    assert(Op.isReg());
+    auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
+    assert(AllowedRegs.size() == ForbiddenRegs.size());
+    for (auto I : ForbiddenRegs.set_bits())
+      AllowedRegs.reset(I);
+    AssignedValue = llvm::MCOperand::createReg(randomBit(AllowedRegs));
+    break;
+  }
+  default:
+    break;
+  }
+}
+
 static_assert(std::is_pod<PfmCountersInfo>::value,
               "We shouldn't have dynamic initialization here");
 const PfmCountersInfo PfmCountersInfo::Default = {nullptr, nullptr, nullptr,
                                                   0u};
 
 const PfmCountersInfo &
 ExegesisTarget::getPfmCounters(llvm::StringRef CpuName) const {
   assert(std::is_sorted(

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

 
 private:
   void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override;
 
   unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override;
 
   unsigned getMaxMemoryAccessSize() const override { return 64; }
 
+  void randomizeMCOperand(const Instruction &Instr, const Variable &Var,
+                          llvm::MCOperand &AssignedValue,
+                          const llvm::BitVector &ForbiddenRegs) const override;
+
   void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                           unsigned Offset) const override;
 
   std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
                                      unsigned Reg,
                                      const llvm::APInt &Value) const override;
 
   ArrayRef<unsigned> getUnavailableRegisters() const override {
ExegesisX86Target::getScratchMemoryRegister(const llvm::Triple &TT) const {
   if (!TT.isArch64Bit()) {
     // FIXME: This would require popping from the stack, so we would have to
     // add some additional setup code.
     return 0;
   }
   return TT.isOSWindows() ? llvm::X86::RCX : llvm::X86::RDI;
 }
 
+void ExegesisX86Target::randomizeMCOperand(
+    const Instruction &Instr, const Variable &Var,
+    llvm::MCOperand &AssignedValue,
+    const llvm::BitVector &ForbiddenRegs) const {
+  ExegesisTarget::randomizeMCOperand(Instr, Var, AssignedValue, ForbiddenRegs);
+
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  switch (Op.getExplicitOperandInfo().OperandType) {
+  case llvm::X86::OperandType::OPERAND_COND_CODE:
+    // FIXME: explore all CC variants.
+    AssignedValue = llvm::MCOperand::createImm(1);
+    break;
+  default:
+    break;
+  }
+}
+
 void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
                                            unsigned Reg,
                                            unsigned Offset) const {
   assert(!isInvalidMemoryInstr(IT.Instr) &&
          "fillMemoryOperands requires a valid memory instruction");
   int MemOpIdx = X86II::getMemoryOperandNo(IT.Instr.Description->TSFlags);
   assert(MemOpIdx >= 0 && "invalid memory operand index");
   // getMemoryOperandNo() ignores tied operands, so we have to add them back.