[X86] Teach RMW with flags isel matching to handle negate

[craig.topper]

Summary

Negate updates flags like a subtract. We should be able to use the flags from the RMW form of negate when we have (store (X86ISD::SUB 0, load A), A)

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::foldLoadStoreIntoMemOperand(SDNode *Node) {
   // and opcode we can handle. Note that this must match the code below that
   // actually lowers the opcodes.
   EVT MemVT = StoreNode->getMemoryVT();
   if (MemVT != MVT::i64 && MemVT != MVT::i32 && MemVT != MVT::i16 &&
       MemVT != MVT::i8)
     return false;
 
   bool IsCommutable = false;
+  bool IsNegate = false;
   switch (Opc) {
   default:
     return false;
   case X86ISD::SUB:
+    IsNegate = isNullConstant(StoredVal.getOperand(0));
+    break;
   case X86ISD::SBB:
     break;
   case X86ISD::ADD:
   case X86ISD::ADC:
   case X86ISD::AND:
   case X86ISD::OR:
   case X86ISD::XOR:
     IsCommutable = true;
     break;
   }
 
-  unsigned LoadOpNo = 0;
+  unsigned LoadOpNo = IsNegate ? 1 : 0;
   LoadSDNode *LoadNode = nullptr;
   SDValue InputChain;
   if (!isFusableLoadOpStorePattern(StoreNode, StoredVal, CurDAG, LoadOpNo,
                                    LoadNode, InputChain)) {
     if (!IsCommutable)
       return false;
 
     // This operation is commutable, try the other operand.
case MVT::i8:
       return Opc8;
     default:
       llvm_unreachable("Invalid size!");
     }
   };
 
   MachineSDNode *Result;
   switch (Opc) {
-  case X86ISD::ADD:
   case X86ISD::SUB:
+    // Handle negate.
+    if (IsNegate) {
+      unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m,
+                                     X86::NEG8m);
+      const SDValue Ops[] = {Base, Scale, Index, Disp, Segment, InputChain};
+      Result = CurDAG->getMachineNode(NewOpc, SDLoc(Node), MVT::i32,
+                                      MVT::Other, Ops);
+      break;
+    }
+   LLVM_FALLTHROUGH;
+  case X86ISD::ADD:
     // Try to match inc/dec.
     if (!Subtarget->slowIncDec() || OptForSize) {
       bool IsOne = isOneConstant(StoredVal.getOperand(1));
       bool IsNegOne = isAllOnesConstant(StoredVal.getOperand(1));
       // ADD/SUB with 1/-1 and carry flag isn't used can use inc/dec.
       if ((IsOne || IsNegOne) && hasNoCarryFlagUses(StoredVal.getValue(1))) {
         unsigned NewOpc = 
           ((Opc == X86ISD::ADD) == IsOne)

llvm/test/CodeGen/X86/fold-rmw-ops.ll

 b:
   tail call void @b()
   ret void
 }
 
 define void @neg64_br() nounwind {
 ; CHECK-LABEL: neg64_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT:    subq {{.*}}(%rip), %rax # encoding: [0x48,0x2b,0x05,A,A,A,A]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte_relax_rex
-; CHECK-NEXT:    movq %rax, {{.*}}(%rip) # encoding: [0x48,0x89,0x05,A,A,A,A]
+; CHECK-NEXT:    negq {{.*}}(%rip) # encoding: [0x48,0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    js .LBB76_1 # encoding: [0x78,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB76_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB76_1: # %a

 b:
   tail call void @b()
   ret void
 }
 
 define void @neg32_br() nounwind {
 ; CHECK-LABEL: neg32_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT:    subl {{.*}}(%rip), %eax # encoding: [0x2b,0x05,A,A,A,A]
-; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    movl %eax, {{.*}}(%rip) # encoding: [0x89,0x05,A,A,A,A]
+; CHECK-NEXT:    negl {{.*}}(%rip) # encoding: [0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    js .LBB77_1 # encoding: [0x78,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB77_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB77_1: # %a

 b:
   tail call void @b()
   ret void
 }
 
 define void @neg16_br() nounwind {
 ; CHECK-LABEL: neg16_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT:    subw {{.*}}(%rip), %ax # encoding: [0x66,0x2b,0x05,A,A,A,A]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    movw %ax, {{.*}}(%rip) # encoding: [0x66,0x89,0x05,A,A,A,A]
+; CHECK-NEXT:    negw {{.*}}(%rip) # encoding: [0x66,0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    js .LBB78_1 # encoding: [0x78,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB78_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB78_1: # %a

 b:
   tail call void @b()
   ret void
 }
 
 define void @neg8_br() nounwind {
 ; CHECK-LABEL: neg8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT:    subb {{.*}}(%rip), %al # encoding: [0x2a,0x05,A,A,A,A]
-; CHECK-NEXT:    # fixup A - offset: 2, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    movb %al, {{.*}}(%rip) # encoding: [0x88,0x05,A,A,A,A]
+; CHECK-NEXT:    negb {{.*}}(%rip) # encoding: [0xf6,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-4, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    js .LBB79_1 # encoding: [0x78,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB79_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB79_1: # %a