AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics

[arsenm]

Summary

The offset operand index is different for atomics.

[arsenm]

Fix run line

[rampitec]

LGTM

[hakzsam]

Thanks for the quick fix Matt!

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

178–179

These should use the NumDefs from the instr desc in case the no-ret atomics are used, although those are inserted later currently

181

The index used needs to be fixed for inst 1

[arsenm]

r357073

lib/Target/AMDGPU/SIInstrInfo.cpp

if (isDS(Opc0) && isDS(Opc1)) {
 
     // Check base reg.
     if (Load0->getOperand(0) != Load1->getOperand(0))
       return false;
 
     // Skip read2 / write2 variants for simplicity.
     // TODO: We should report true if the used offsets are adjacent (excluded
     // st64 versions).
-    if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
-        AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
+    int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
+    int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
+    if (Offset0Idx == -1 || Offset1Idx == -1)
       return false;
 
-    Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
-    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
+    // getNamedOperandIdx returns the index for MachineInstrs.  Since they
+    // include the output in the operand list, but SDNodes don't, we need to
+    // subtract the index by one.
+    --Offset0Idx;
+    --Offset1Idx;
+    Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
+    Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset0Idx))->getZExtValue();
     return true;
   }
 
   if (isSMRD(Opc0) && isSMRD(Opc1)) {
     // Skip time and cache invalidation instructions.
     if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
         AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
       return false;

test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; TII::areLoadsFromSameBasePtr failed because the offset for atomics
+; is different from a normal load due to the data operand.
+
+; GCN-LABEL: {{^}}are_loads_from_same_base_ptr_ds_atomic:
+; GCN: global_load_dword
+; GCN: ds_min_u32
+; GCN: ds_max_u32
+define amdgpu_kernel void @are_loads_from_same_base_ptr_ds_atomic(i32 addrspace(1)* %arg0, i32 addrspace(3)* noalias %ptr0) #0 {
+  %tmp1 = load volatile i32, i32 addrspace(1)* %arg0
+  %tmp2 = atomicrmw umin i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst
+  %tmp3 = atomicrmw umax i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst
+  ret void
+}
+
+attributes #0 = { nounwind }