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[ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.
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Authored by efriedma on Mar 19 2019, 4:36 PM.

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Summary

This takes sequences like "mov r4, sp; str r0, [r4]", and optimizes them to something like "str r0, [sp]".

For regular stack variables, this optimization was already implemented: we lower loads and stores using frame indexes, which are expanded later. However, when constructing a call frame for a call with more than four arguments, the existing optimization doesn't apply. We need to use stores which are actually relative to the current value of sp, and don't have an associated frame index.

This patch adds a special case to handle that construct. At the DAG level, this is an ISD::STORE where the address is a CopyFromReg from SP (plus a small constant offset).

This applies only to Thumb1: in Thumb2 or ARM mode, a regular store instruction can access SP directly, so the COPY gets eliminated by existing code.

The change to ARMDAGToDAGISel::SelectThumbAddrModeSP is a related cleanup: we shouldn't pretend that it can select anything other than frame indexes.

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rL LLVM

Event Timeline

efriedma created this revision.Mar 19 2019, 4:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 19 2019, 4:36 PM
This revision is now accepted and ready to land.Mar 20 2019, 3:00 AM
This revision was automatically updated to reflect the committed changes.