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[RISCV] Add basic RV32E definitions and MC layer support
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Authored by asb on Mar 17 2019, 5:12 AM.

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Summary

The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E.

Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC).

Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches.

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rL LLVM

Event Timeline

asb created this revision.Mar 17 2019, 5:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 17 2019, 5:12 AM
apazos added inline comments.Mar 20 2019, 2:52 PM
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
78 ↗(On Diff #191014)

This RegNo is the index to the table, not the value RISCV::X*. But in RISCVAsmParser.cpp matchRegisterNameHelpe and ParseRegister RegNo is that value. Maybe it should be called just Reg in those functions to avoid confusion

Thanks Alex, LGTM

This revision was not accepted when it landed; it landed in state Needs Review.Mar 22 2019, 4:23 AM
This revision was automatically updated to reflect the committed changes.