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[RISCV] Add basic RV32E definitions and MC layer support
The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470 llvm-svn: 356744
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; RUN: not llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ | ||
; RUN: | FileCheck -check-prefix=RV64E %s | ||
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; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target |
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; RUN: not llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s | ||
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; CHECK: LLVM ERROR: Codegen not yet implemented for RV32E | ||
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define void @nothing() nounwind { | ||
ret void | ||
} |
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# RUN: not llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ | ||
# RUN: | FileCheck %s -check-prefix=RV64E | ||
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# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target |
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# RUN: not llvm-mc -triple riscv32 -mattr=+e < %s 2>&1 | FileCheck %s | ||
# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ | ||
# RUN: | llvm-objdump -mattr=+e -riscv-no-aliases -d -r - \ | ||
# RUN: | FileCheck -check-prefix=CHECK-DIS %s | ||
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# Perform a simple sanity check that registers x16-x31 (and the equivalent | ||
# ABI names) are rejected for RV32E, when both assembling and disassembling. | ||
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# CHECK-DIS: 37 18 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x16, 1 | ||
# CHECK-DIS: b7 28 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x17, 2 | ||
# CHECK-DIS: 37 39 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x18, 3 | ||
# CHECK-DIS: b7 49 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x19, 4 | ||
# CHECK-DIS: 37 5a 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x20, 5 | ||
# CHECK-DIS: b7 6a 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x21, 6 | ||
# CHECK-DIS: 37 7b 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x22, 7 | ||
# CHECK-DIS: b7 8b 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x23, 8 | ||
# CHECK-DIS: 37 9c 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x24, 9 | ||
# CHECK-DIS: b7 ac 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x25, 10 | ||
# CHECK-DIS: 37 bd 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x26, 11 | ||
# CHECK-DIS: b7 cd 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x27, 12 | ||
# CHECK-DIS: 37 de 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x28, 13 | ||
# CHECK-DIS: b7 ee 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x29, 14 | ||
# CHECK-DIS: 37 ff 00 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x30, 15 | ||
# CHECK-DIS: b7 0f 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction | ||
lui x31, 16 | ||
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# CHECK-DIS: 17 18 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc a6, 17 | ||
# CHECK-DIS: 97 28 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc a7, 18 | ||
# CHECK-DIS: 17 39 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s2, 19 | ||
# CHECK-DIS: 97 49 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s3, 20 | ||
# CHECK-DIS: 17 5a 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s4, 21 | ||
# CHECK-DIS: 97 6a 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s5, 22 | ||
# CHECK-DIS: 17 7b 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s6, 23 | ||
# CHECK-DIS: 97 8b 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s7, 24 | ||
# CHECK-DIS: 17 9c 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s8, 25 | ||
# CHECK-DIS: 97 ac 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s9, 26 | ||
# CHECK-DIS: 17 bd 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s10, 27 | ||
# CHECK-DIS: 97 cd 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc s11, 28 | ||
# CHECK-DIS: 17 de 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc t3, 29 | ||
# CHECK-DIS: 97 ee 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc t4, 30 | ||
# CHECK-DIS: 17 ff 01 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc t5, 31 | ||
# CHECK-DIS: 97 0f 02 00 <unknown> | ||
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction | ||
auipc t6, 32 |
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# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \ | ||
# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s | ||
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \ | ||
# RUN: | llvm-objdump -riscv-no-aliases -d -r - \ | ||
# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s | ||
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# This file provides a basic sanity check for RV32E, checking that the expected | ||
# set of registers and instructions are accepted. | ||
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# CHECK-ASM-AND-OBJ: lui zero, 1 | ||
lui x0, 1 | ||
# CHECK-ASM-AND-OBJ: auipc ra, 2 | ||
auipc x1, 2 | ||
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# CHECK-ASM-AND-OBJ: jal sp, 4 | ||
jal x2, 4 | ||
# CHECK-ASM-AND-OBJ: jalr gp, gp, 4 | ||
jalr x3, x3, 4 | ||
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# CHECK-ASM-AND-OBJ: beq tp, t0, 8 | ||
beq x4, x5, 8 | ||
# CHECK-ASM-AND-OBJ: bne t1, t2, 12 | ||
bne x6, x7, 12 | ||
# CHECK-ASM-AND-OBJ: blt s0, s1, 16 | ||
blt x8, x9, 16 | ||
# CHECK-ASM-AND-OBJ: bge a0, a1, 20 | ||
bge x10, x11, 20 | ||
# CHECK-ASM-AND-OBJ: bgeu a2, a3, 24 | ||
bgeu x12, x13, 24 | ||
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# CHECK-ASM-AND-OBJ: lb a4, 25(a5) | ||
lb x14, 25(x15) | ||
# CHECK-ASM-AND-OBJ: lh zero, 26(ra) | ||
lh zero, 26(ra) | ||
# CHECK-ASM-AND-OBJ: lw sp, 28(gp) | ||
lw sp, 28(gp) | ||
# CHECK-ASM-AND-OBJ: lbu tp, 29(t0) | ||
lbu tp, 29(t0) | ||
# CHECK-ASM-AND-OBJ: lhu t1, 30(t2) | ||
lhu t1, 30(t2) | ||
# CHECK-ASM-AND-OBJ: sb s0, 31(s1) | ||
sb s0, 31(s1) | ||
# CHECK-ASM-AND-OBJ: sh a0, 32(a1) | ||
sh a0, 32(a1) | ||
# CHECK-ASM-AND-OBJ: sw a2, 36(a3) | ||
sw a2, 36(a3) | ||
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# CHECK-ASM-AND-OBJ: addi a4, a5, 37 | ||
addi a4, a5, 37 | ||
# CHECK-ASM-AND-OBJ: slti a0, a2, -20 | ||
slti a0, a2, -20 | ||
# CHECK-ASM-AND-OBJ: xori tp, t1, -99 | ||
xori tp, t1, -99 | ||
# CHECK-ASM-AND-OBJ: ori a0, a1, -2048 | ||
ori a0, a1, -2048 | ||
# CHECK-ASM-AND-OBJ: andi ra, sp, 2047 | ||
andi ra, sp, 2047 | ||
# CHECK-ASM-AND-OBJ: slli t1, t1, 31 | ||
slli t1, t1, 31 | ||
# CHECK-ASM-AND-OBJ: srli a0, a4, 0 | ||
srli a0, a4, 0 | ||
# CHECK-ASM-AND-OBJ: srai a1, sp, 15 | ||
srai a1, sp, 15 | ||
# CHECK-ASM-AND-OBJ: slli t0, t1, 13 | ||
slli t0, t1, 13 | ||
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# CHECK-ASM-AND-OBJ: add ra, zero, zero | ||
add ra, zero, zero | ||
# CHECK-ASM-AND-OBJ: sub t0, t2, t1 | ||
sub t0, t2, t1 | ||
# CHECK-ASM-AND-OBJ: sll a5, a4, a3 | ||
sll a5, a4, a3 | ||
# CHECK-ASM-AND-OBJ: slt s0, s0, s0 | ||
slt s0, s0, s0 | ||
# CHECK-ASM-AND-OBJ: sltu gp, a0, a1 | ||
sltu gp, a0, a1 | ||
# CHECK-ASM-AND-OBJ: xor s1, s0, s1 | ||
xor s1, s0, s1 | ||
# CHECK-ASM-AND-OBJ: srl a0, s0, t0 | ||
srl a0, s0, t0 | ||
# CHECK-ASM-AND-OBJ: sra t0, a3, zero | ||
sra t0, a3, zero | ||
# CHECK-ASM-AND-OBJ: or a5, t1, ra | ||
or a5, t1, ra | ||
# CHECK-ASM-AND-OBJ: and a0, s1, a3 | ||
and a0, s1, a3 | ||
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# CHECK-ASM-AND-OBJ: fence iorw, iorw | ||
fence iorw, iorw | ||
# CHECK-ASM-AND-OBJ: fence.tso | ||
fence.tso | ||
# CHECK-ASM-AND-OBJ: fence.i | ||
fence.i | ||
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# CHECK-ASM-AND-OBJ: ecall | ||
ecall | ||
# CHECK-ASM-AND-OBJ: ebreak | ||
ebreak | ||
# CHECK-ASM-AND-OBJ: unimp | ||
unimp | ||
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# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 | ||
csrrw t0, 0xfff, t1 | ||
# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero | ||
csrrs s0, 0xc00, x0 | ||
# CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5 | ||
csrrs s0, 0x001, a5 | ||
# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra | ||
csrrc sp, 0x000, ra | ||
# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 | ||
csrrwi a5, 0x000, 0 | ||
# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 | ||
csrrsi t2, 0xfff, 31 | ||
# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 | ||
csrrci t1, 0x140, 5 |
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