[AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector

[paquette]

Summary

NFC.

Some more preliminary factoring for G_INSERT_VECTOR_ELT. The lambda there can be replaced by existing functions. We'll need the same code for G_INSERT_VECTOR_ELT, so this will allow us to avoid copying/pasting the lambda.

[aemerson]

LGTM.

llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
     PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
                               MIRBuilder);
     DstVec = PrevMI->getOperand(0).getReg();
   }
 
   // If DstTy's size in bits is less than 128, then emit a subregister copy
   // from DstVec to the last register we've defined.
   if (DstSize < 128) {
-    unsigned SubReg = 0;
-
-    // Helper lambda to decide on a register class and subregister for the
-    // subregister copy.
-    auto GetRegInfoForCopy = [&SubReg,
-                              &DstSize]() -> const TargetRegisterClass * {
-      switch (DstSize) {
-      default:
-        LLVM_DEBUG(dbgs() << "Unknown destination size (" << DstSize << ")\n");
-        return nullptr;
-      case 32:
-        SubReg = AArch64::ssub;
-        return &AArch64::FPR32RegClass;
-      case 64:
-        SubReg = AArch64::dsub;
-        return &AArch64::FPR64RegClass;
-      }
-    };
+    // Force this to be FPR using the destination vector.
+    const TargetRegisterClass *RC =
+        getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
+    if (!RC)
+      return false;
+    if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
+      LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
+      return false;
 
-    const TargetRegisterClass *RC = GetRegInfoForCopy();
-    if (!RC)
+    unsigned SubReg = 0;
+    if (!getSubRegForClass(RC, TRI, SubReg))
       return false;
+    if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
+      LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << DstSize
+                        << "\n");
+      return false;
+    }
 
     unsigned Reg = MRI.createVirtualRegister(RC);
     unsigned DstReg = I.getOperand(0).getReg();
 
     // MIRBuilder doesn't let us create uses with subregs & flags, so use
     // BuildMI here instead.
     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
             DstReg)