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Differential D59308

[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
ClosedPublic

Authored by craig.topper on Mar 13 2019, 10:22 AM.

Details

Reviewers
jfb
RKSimon
spatel
Commits
rG84abec2855ad: [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
rL356078: [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
Summary

The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.

We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.

I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Mar 13 2019, 10:22 AM
Herald added subscribers: jdoerfert, JDevlieghere. · View Herald TranscriptMar 13 2019, 10:22 AM
jfb accepted this revision.Mar 13 2019, 10:34 AM

I think this is fine since it makes something less broken, and is consistent with your other patch on the clang side. Would be neat for someone else to double-check.

This revision is now accepted and ready to land.Mar 13 2019, 10:34 AM
RKSimon accepted this revision.Mar 13 2019, 11:23 AM

LGTM

Closed by commit rL356078: [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() (authored by ctopper). · Explain WhyMar 13 2019, 11:47 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMar 13 2019, 11:47 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
2 lines
2 lines
2 lines
test/
CodeGen/
X86/
578 lines
27 lines

Diff 190463

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 27,203 Lines • ▼ Show 20 Linesvoid X86TargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::READCYCLECOUNTER: { case ISD::READCYCLECOUNTER: {
return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget, return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
Results); Results);
} }
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: { case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
EVT T = N->getValueType(0); EVT T = N->getValueType(0);
assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
bool Regs64bit = T == MVT::i128; bool Regs64bit = T == MVT::i128;
assert((!Regs64bit || Subtarget.hasCmpxchg16b()) &&
"64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS requires CMPXCHG16B");
MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
SDValue cpInL, cpInH; SDValue cpInL, cpInH;
cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
DAG.getConstant(0, dl, HalfT)); DAG.getConstant(0, dl, HalfT));
cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
DAG.getConstant(1, dl, HalfT)); DAG.getConstant(1, dl, HalfT));
cpInL = DAG.getCopyToReg(N->getOperand(0), dl, cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
Regs64bit ? X86::RAX : X86::EAX, Regs64bit ? X86::RAX : X86::EAX,
▲ Show 20 Lines • Show All 16,527 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86InstrInfo.td

Show First 20 Lines • Show All 2,088 Lines • ▼ Show 20 Lines
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
"cmpxchg8b\t$dst", []>, TB; "cmpxchg8b\t$dst", []>, TB;
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
"cmpxchg16b\t$dst", []>, "cmpxchg16b\t$dst", []>,
TB, Requires<[HasCmpxchg16b, In64BitMode]>; TB, Requires<[HasCmpxchg16b]>;
} // SchedRW, mayLoad, mayStore, hasSideEffects } // SchedRW, mayLoad, mayStore, hasSideEffects
// Lock instruction prefix // Lock instruction prefix
let SchedRW = [WriteMicrocoded] in let SchedRW = [WriteMicrocoded] in
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
let SchedRW = [WriteNop] in { let SchedRW = [WriteNop] in {
▲ Show 20 Lines • Show All 1,376 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86Subtarget.h

Show First 20 Lines • Show All 614 Lines • ▼ Show 20 Linespublic:
bool isSHLDSlow() const { return IsSHLDSlow; } bool isSHLDSlow() const { return IsSHLDSlow; }
bool isPMULLDSlow() const { return IsPMULLDSlow; } bool isPMULLDSlow() const { return IsPMULLDSlow; }
bool isPMADDWDSlow() const { return IsPMADDWDSlow; } bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
int getGatherOverhead() const { return GatherOverhead; } int getGatherOverhead() const { return GatherOverhead; }
int getScatterOverhead() const { return ScatterOverhead; } int getScatterOverhead() const { return ScatterOverhead; }
bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
bool hasCmpxchg16b() const { return HasCmpxchg16b; } bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
bool useLeaForSP() const { return UseLeaForSP; } bool useLeaForSP() const { return UseLeaForSP; }
bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; } bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; } bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
bool hasFastVariableShuffle() const { bool hasFastVariableShuffle() const {
return HasFastVariableShuffle; return HasFastVariableShuffle;
} }
bool hasFastPartialYMMorZMMWrite() const { bool hasFastPartialYMMorZMMWrite() const {
return HasFastPartialYMMorZMMWrite; return HasFastPartialYMMorZMMWrite;
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/atomic128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck %s -check-prefixes=CHECK32
; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=-cx16 | FileCheck %s -check-prefixes=CHECK32
@var = global i128 0 @var = global i128 0
; Due to the scheduling right after isel for cmpxchg and given the ; Due to the scheduling right after isel for cmpxchg and given the
; machine scheduler and copy coalescer do not mess up with physical ; machine scheduler and copy coalescer do not mess up with physical
; register live-ranges, we end up with a useless copy. ; register live-ranges, we end up with a useless copy.
define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) { define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
; CHECK-LABEL: val_compare_and_swap: ; CHECK-LABEL: val_compare_and_swap:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rcx, %rbx ; CHECK-NEXT: movq %rcx, %rbx
; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: movq %r8, %rcx ; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: val_compare_and_swap:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
ret i128 %val ret i128 %val
} }
define void @fetch_and_nand(i128* %p, i128 %bits) { define void @fetch_and_nand(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_nand: ; CHECK-LABEL: fetch_and_nand:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 14 Lines
; CHECK-NEXT: notq %rcx ; CHECK-NEXT: notq %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB1_1 ; CHECK-NEXT: jne LBB1_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_nand:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_nand_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw nand i128* %p, i128 %bits release %val = atomicrmw nand i128* %p, i128 %bits release
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_or(i128* %p, i128 %bits) { define void @fetch_and_or(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_or: ; CHECK-LABEL: fetch_and_or:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 12 Lines
; CHECK-NEXT: orq %r8, %rcx ; CHECK-NEXT: orq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB2_1 ; CHECK-NEXT: jne LBB2_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_or:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_or_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw or i128* %p, i128 %bits seq_cst %val = atomicrmw or i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_add(i128* %p, i128 %bits) { define void @fetch_and_add(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_add: ; CHECK-LABEL: fetch_and_add:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 12 Lines
; CHECK-NEXT: adcq %r8, %rcx ; CHECK-NEXT: adcq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB3_1 ; CHECK-NEXT: jne LBB3_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_add:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_add_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw add i128* %p, i128 %bits seq_cst %val = atomicrmw add i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_sub(i128* %p, i128 %bits) { define void @fetch_and_sub(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_sub: ; CHECK-LABEL: fetch_and_sub:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 12 Lines
; CHECK-NEXT: sbbq %r8, %rcx ; CHECK-NEXT: sbbq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB4_1 ; CHECK-NEXT: jne LBB4_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_sub:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_sub_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw sub i128* %p, i128 %bits seq_cst %val = atomicrmw sub i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_min(i128* %p, i128 %bits) { define void @fetch_and_min(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_min: ; CHECK-LABEL: fetch_and_min:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 15 Lines
; CHECK-NEXT: cmovgeq %rax, %rbx ; CHECK-NEXT: cmovgeq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB5_1 ; CHECK-NEXT: jne LBB5_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_min:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_min_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw min i128* %p, i128 %bits seq_cst %val = atomicrmw min i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_max(i128* %p, i128 %bits) { define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_max: ; CHECK-LABEL: fetch_and_max:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 15 Lines
; CHECK-NEXT: cmovgeq %rax, %rbx ; CHECK-NEXT: cmovgeq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB6_1 ; CHECK-NEXT: jne LBB6_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_max:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_max_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw max i128* %p, i128 %bits seq_cst %val = atomicrmw max i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_umin(i128* %p, i128 %bits) { define void @fetch_and_umin(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umin: ; CHECK-LABEL: fetch_and_umin:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 15 Lines
; CHECK-NEXT: cmovaeq %rax, %rbx ; CHECK-NEXT: cmovaeq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB7_1 ; CHECK-NEXT: jne LBB7_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_umin:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_umin_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw umin i128* %p, i128 %bits seq_cst %val = atomicrmw umin i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_umax(i128* %p, i128 %bits) { define void @fetch_and_umax(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umax: ; CHECK-LABEL: fetch_and_umax:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
Show All 15 Lines
; CHECK-NEXT: cmovbq %rax, %rbx ; CHECK-NEXT: cmovbq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB8_1 ; CHECK-NEXT: jne LBB8_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: fetch_and_umax:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_umax_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
%val = atomicrmw umax i128* %p, i128 %bits seq_cst %val = atomicrmw umax i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define i128 @atomic_load_seq_cst(i128* %p) { define i128 @atomic_load_seq_cst(i128* %p) {
; CHECK-LABEL: atomic_load_seq_cst: ; CHECK-LABEL: atomic_load_seq_cst:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: atomic_load_seq_cst:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
%r = load atomic i128, i128* %p seq_cst, align 16 %r = load atomic i128, i128* %p seq_cst, align 16
ret i128 %r ret i128 %r
} }
define i128 @atomic_load_relaxed(i128* %p) { define i128 @atomic_load_relaxed(i128* %p) {
; CHECK-LABEL: atomic_load_relaxed: ; CHECK-LABEL: atomic_load_relaxed:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: atomic_load_relaxed:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
%r = load atomic i128, i128* %p monotonic, align 16 %r = load atomic i128, i128* %p monotonic, align 16
ret i128 %r ret i128 %r
} }
define void @atomic_store_seq_cst(i128* %p, i128 %in) { define void @atomic_store_seq_cst(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_seq_cst: ; CHECK-LABEL: atomic_store_seq_cst:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB11_1: ## %atomicrmw.start ; CHECK-NEXT: LBB11_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB11_1 ; CHECK-NEXT: jne LBB11_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: atomic_store_seq_cst:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
store atomic i128 %in, i128* %p seq_cst, align 16 store atomic i128 %in, i128* %p seq_cst, align 16
ret void ret void
} }
define void @atomic_store_release(i128* %p, i128 %in) { define void @atomic_store_release(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_release: ; CHECK-LABEL: atomic_store_release:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB12_1: ## %atomicrmw.start ; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB12_1 ; CHECK-NEXT: jne LBB12_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: atomic_store_release:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
store atomic i128 %in, i128* %p release, align 16 store atomic i128 %in, i128* %p release, align 16
ret void ret void
} }
define void @atomic_store_relaxed(i128* %p, i128 %in) { define void @atomic_store_relaxed(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_relaxed: ; CHECK-LABEL: atomic_store_relaxed:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB13_1: ## %atomicrmw.start ; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB13_1 ; CHECK-NEXT: jne LBB13_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end ; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; CHECK32-LABEL: atomic_store_relaxed:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
store atomic i128 %in, i128* %p unordered, align 16 store atomic i128 %in, i128* %p unordered, align 16
ret void ret void
} }
@fsc128 = external global fp128
define void @atomic_fetch_swapf128(fp128 %x) nounwind {
; CHECK-LABEL: atomic_fetch_swapf128:
; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq %rsi, %rcx
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
; CHECK-NEXT: movq (%rsi), %rax
; CHECK-NEXT: movq 8(%rsi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB14_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rsi)
; CHECK-NEXT: jne LBB14_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
%t1 = atomicrmw xchg fp128* @fsc128, fp128 %x acquire
ret void
}

llvm/trunk/test/CodeGen/X86/atomicf128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
; FIXME: This test has a fatal error in 32-bit mode
@fsc128 = external global fp128
define void @atomic_fetch_swapf128(fp128 %x) nounwind {
; CHECK-LABEL: atomic_fetch_swapf128:
; CHECK: ## %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq %rsi, %rcx
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
; CHECK-NEXT: movq (%rsi), %rax
; CHECK-NEXT: movq 8(%rsi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rsi)
; CHECK-NEXT: jne LBB0_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
%t1 = atomicrmw xchg fp128* @fsc128, fp128 %x acquire
ret void
}