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[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1
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Authored by aemerson on Feb 26 2019, 9:46 AM.

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Summary

This extends the existing support for shufflevector to handle cases like <2 x float>, which we can implement by concating the vectors and using a TBL1.

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rL LLVM

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aemerson created this revision.Feb 26 2019, 9:46 AM
paquette added inline comments.Feb 26 2019, 3:04 PM
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
1979 ↗(On Diff #188398)

Is it possible that EltSize could be something invalid when it's coming into here? Should we have some error-handling?

1981 ↗(On Diff #188398)

Not important for this patch, but I've noticed that we have a lot of this subregister calculation code floating around.

Might be good to migrate some of this over to using a utility function for calculating the subregister index. getSubRegForClass does it, but I don't know if that's the best choice.

aemerson marked 2 inline comments as done.Feb 26 2019, 3:11 PM
aemerson added inline comments.
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
1979 ↗(On Diff #188398)

Yeah I can add llvm_unreachable() to catch the unexpected cases. We shouldn't be seeing anything else here I think.

1981 ↗(On Diff #188398)

Yes I considered using that, but it was expecting a RegClass (and also has a special case for gpr32). I agree we'll want to have some common internal API to get this information in future.

aemerson updated this revision to Diff 188470.Feb 26 2019, 3:15 PM

Explicitly check for valid element sizes or error out if not valid.

This revision is now accepted and ready to land.Feb 27 2019, 8:07 AM
This revision was automatically updated to reflect the committed changes.