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[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1.

Description

[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1.

This extends the existing support for shufflevector to handle cases like
<2 x float>, which we can implement by concating the vectors and using a TBL1.

Differential Revision: https://reviews.llvm.org/D58684