[X86] Lower ISD::UADDO to use the Z flag instead of C flag when the RHS is a constant 1 to encourage INC formation.

[craig.topper]

Summary

Add an additional combine to combineCarryThroughADD to reverse it back to the C flag.

I believe this catches the cases that D57547 got.

[spatel]

LGTM. Just checking if I'm seeing this correctly: the 2 changes are independent and have their own shares of the test diffs?

[craig.topper]

The combineCarryThroughADD prevents some regressions from the getX86XALUOOp change. But I think it picked up a change to at least codegen-prepare-uaddo.ll by itself. I can commit the combineCarryThroughADD separately first if you want.

[spatel]

In D57637#1382186, @craig.topper wrote:

The combineCarryThroughADD prevents some regressions from the getX86XALUOOp change. But I think it picked up a change to at least codegen-prepare-uaddo.ll by itself. I can commit the combineCarryThroughADD separately first if you want.

No need to intro regressions - I noticed regressions to the alternate proposal in D57547 when I extended that to handle COND_B --> COND_E, so I was just wondering if this was avoiding that. Might be a potential follow-up for a USUBO / dec sibling to this? Not sure if we have as much test coverage for those.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

getX86XALUOOp(X86::CondCode &Cond, SDValue Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default: llvm_unreachable("Unknown ovf instruction!");
   case ISD::SADDO:
     BaseOp = X86ISD::ADD;
     Cond = X86::COND_O;
     break;
   case ISD::UADDO:
     BaseOp = X86ISD::ADD;
-    Cond = X86::COND_B;
+    Cond = isOneConstant(RHS) ? X86::COND_E : X86::COND_B;
     break;
   case ISD::SSUBO:
     BaseOp = X86ISD::SUB;
     Cond = X86::COND_O;
     break;
   case ISD::USUBO:
     BaseOp = X86ISD::SUB;
     Cond = X86::COND_B;
if (isAllOnesConstant(EFLAGS.getOperand(1))) {
               CarryOp1.getValueType().isInteger() &&
               !isa<ConstantSDNode>(CarryOp1.getOperand(1))) {
             SDValue SubCommute =
                 DAG.getNode(X86ISD::SUB, SDLoc(CarryOp1), CarryOp1->getVTList(),
                             CarryOp1.getOperand(1), CarryOp1.getOperand(0));
             return SDValue(SubCommute.getNode(), CarryOp1.getResNo());
           }
         }
+        // If this is a check of the z flag of an add with 1, switch to the
+        // C flag.
+        if (CarryCC == X86::COND_E &&
+            CarryOp1.getOpcode() == X86ISD::ADD &&
+            isOneConstant(CarryOp1.getOperand(1)))
+          return CarryOp1;
       }
     }
   }
 
   return SDValue();
 }
 
 /// Optimize an EFLAGS definition used according to the condition code \p CC

llvm/trunk/test/CodeGen/X86/codegen-prepare-uaddo.ll

; CHECK-NEXT:    retq
   %5 = extractvalue { i8, i64 } %4, 1
   store i64 %5, i64* %1, align 8
   ret void
 }
 
 define void @test_1(i64*, i64*) {
 ; CHECK-LABEL: test_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    incq (%rdi)
-; CHECK-NEXT:    sete %al
-; CHECK-NEXT:    addb $-1, %al
+; CHECK-NEXT:    addq $1, (%rdi)
 ; CHECK-NEXT:    adcq $0, (%rsi)
 ; CHECK-NEXT:    retq
   %3 = load i64, i64* %0, align 8
   %4 = add i64 %3, 1
   store i64 %4, i64* %0, align 8
   %5 = icmp eq i64 %4, 0
   %6 = zext i1 %5 to i8
   %7 = load i64, i64* %1, align 8

llvm/trunk/test/CodeGen/X86/combine-add-usat.ll

; AVX-NEXT:    retq
   %res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)
   ret <8 x i16> %res
 }
 
 ; fold (uadd_sat c, x) -> (add_ssat x, c)
 define i32 @combine_constant_i32(i32 %a0) {
 ; CHECK-LABEL: combine_constant_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addl $1, %edi
+; CHECK-NEXT:    incl %edi
 ; CHECK-NEXT:    movl $-1, %eax
-; CHECK-NEXT:    cmovael %edi, %eax
+; CHECK-NEXT:    cmovnel %edi, %eax
 ; CHECK-NEXT:    retq
   %1 = call i32 @llvm.uadd.sat.i32(i32 1, i32 %a0)
   ret i32 %1
 }
 
 define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {
 ; SSE-LABEL: combine_constant_v8i16:
 ; SSE:       # %bb.0:

llvm/trunk/test/CodeGen/X86/scheduler-backtracking.ll

 
 declare i256 @llvm.ctlz.i256(i256, i1) nounwind readnone
 
 define i64 @test4(i64 %a, i64 %b) nounwind {
 ; ILP-LABEL: test4:
 ; ILP:       # %bb.0:
 ; ILP-NEXT:    xorl %ecx, %ecx
 ; ILP-NEXT:    xorl %edx, %edx
-; ILP-NEXT:    addq $1, %rsi
-; ILP-NEXT:    setb %dl
+; ILP-NEXT:    incq %rsi
+; ILP-NEXT:    sete %dl
 ; ILP-NEXT:    movl $2, %eax
 ; ILP-NEXT:    cmpq %rdi, %rsi
 ; ILP-NEXT:    sbbq $0, %rdx
 ; ILP-NEXT:    movl $0, %edx
 ; ILP-NEXT:    sbbq %rdx, %rdx
 ; ILP-NEXT:    sbbq %rcx, %rcx
 ; ILP-NEXT:    setae %cl
 ; ILP-NEXT:    movzbl %cl, %ecx
 ; ILP-NEXT:    subq %rcx, %rax
 ; ILP-NEXT:    retq
 ;
 ; HYBRID-LABEL: test4:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    xorl %eax, %eax
 ; HYBRID-NEXT:    xorl %ecx, %ecx
-; HYBRID-NEXT:    addq $1, %rsi
-; HYBRID-NEXT:    setb %cl
+; HYBRID-NEXT:    incq %rsi
+; HYBRID-NEXT:    sete %cl
 ; HYBRID-NEXT:    cmpq %rdi, %rsi
 ; HYBRID-NEXT:    sbbq $0, %rcx
 ; HYBRID-NEXT:    movl $0, %ecx
 ; HYBRID-NEXT:    sbbq %rcx, %rcx
 ; HYBRID-NEXT:    sbbq %rax, %rax
 ; HYBRID-NEXT:    setae %al
 ; HYBRID-NEXT:    movzbl %al, %ecx
 ; HYBRID-NEXT:    movl $2, %eax
 ; HYBRID-NEXT:    subq %rcx, %rax
 ; HYBRID-NEXT:    retq
 ;
 ; BURR-LABEL: test4:
 ; BURR:       # %bb.0:
 ; BURR-NEXT:    xorl %eax, %eax
 ; BURR-NEXT:    xorl %ecx, %ecx
-; BURR-NEXT:    addq $1, %rsi
-; BURR-NEXT:    setb %cl
+; BURR-NEXT:    incq %rsi
+; BURR-NEXT:    sete %cl
 ; BURR-NEXT:    cmpq %rdi, %rsi
 ; BURR-NEXT:    sbbq $0, %rcx
 ; BURR-NEXT:    movl $0, %ecx
 ; BURR-NEXT:    sbbq %rcx, %rcx
 ; BURR-NEXT:    sbbq %rax, %rax
 ; BURR-NEXT:    setae %al
 ; BURR-NEXT:    movzbl %al, %ecx
 ; BURR-NEXT:    movl $2, %eax
 ; BURR-NEXT:    subq %rcx, %rax
 ; BURR-NEXT:    retq
 ;
 ; SRC-LABEL: test4:
 ; SRC:       # %bb.0:
 ; SRC-NEXT:    xorl %eax, %eax
-; SRC-NEXT:    addq $1, %rsi
-; SRC-NEXT:    setb %al
+; SRC-NEXT:    incq %rsi
+; SRC-NEXT:    sete %al
 ; SRC-NEXT:    xorl %ecx, %ecx
 ; SRC-NEXT:    cmpq %rdi, %rsi
 ; SRC-NEXT:    sbbq $0, %rax
 ; SRC-NEXT:    movl $0, %eax
 ; SRC-NEXT:    sbbq %rax, %rax
 ; SRC-NEXT:    sbbq %rcx, %rcx
 ; SRC-NEXT:    setae %al
 ; SRC-NEXT:    movzbl %al, %ecx
 ; SRC-NEXT:    movl $2, %eax
 ; SRC-NEXT:    subq %rcx, %rax
 ; SRC-NEXT:    retq
 ;
 ; LIN-LABEL: test4:
 ; LIN:       # %bb.0:
 ; LIN-NEXT:    movl $2, %eax
 ; LIN-NEXT:    xorl %ecx, %ecx
 ; LIN-NEXT:    xorl %edx, %edx
-; LIN-NEXT:    addq $1, %rsi
-; LIN-NEXT:    setb %dl
+; LIN-NEXT:    incq %rsi
+; LIN-NEXT:    sete %dl
 ; LIN-NEXT:    cmpq %rdi, %rsi
 ; LIN-NEXT:    sbbq $0, %rdx
 ; LIN-NEXT:    movl $0, %edx
 ; LIN-NEXT:    sbbq %rdx, %rdx
 ; LIN-NEXT:    sbbq %rcx, %rcx
 ; LIN-NEXT:    setae %cl
 ; LIN-NEXT:    movzbl %cl, %ecx
 ; LIN-NEXT:    subq %rcx, %rax

llvm/trunk/test/CodeGen/X86/slow-incdec.ll

; CHECK-NEXT:    retl
   %r = add i32 %x, -1
   ret i32 %r
 }
 
 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
 declare void @other(i32* ) nounwind;
 
 define void @cond_ae_to_cond_ne(i32* %p) nounwind {
-; CHECK-LABEL: cond_ae_to_cond_ne:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    addl $1, (%eax)
-; CHECK-NEXT:    jae .LBB4_1
-; CHECK-NEXT:  # %bb.2: # %if.end4
-; CHECK-NEXT:    jmp other # TAILCALL
-; CHECK-NEXT:  .LBB4_1: # %return
-; CHECK-NEXT:    retl
+; INCDEC-LABEL: cond_ae_to_cond_ne:
+; INCDEC:       # %bb.0: # %entry
+; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; INCDEC-NEXT:    incl (%eax)
+; INCDEC-NEXT:    jne .LBB4_1
+; INCDEC-NEXT:  # %bb.2: # %if.end4
+; INCDEC-NEXT:    jmp other # TAILCALL
+; INCDEC-NEXT:  .LBB4_1: # %return
+; INCDEC-NEXT:    retl
+;
+; ADD-LABEL: cond_ae_to_cond_ne:
+; ADD:       # %bb.0: # %entry
+; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; ADD-NEXT:    addl $1, (%eax)
+; ADD-NEXT:    jne .LBB4_1
+; ADD-NEXT:  # %bb.2: # %if.end4
+; ADD-NEXT:    jmp other # TAILCALL
+; ADD-NEXT:  .LBB4_1: # %return
+; ADD-NEXT:    retl
 entry:
   %t0 = load i32, i32* %p, align 8
   %add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %t0, i32 1)
   %inc = extractvalue { i32, i1 } %add_ov, 0
   store i32 %inc, i32* %p, align 8
   %ov = extractvalue { i32, i1 } %add_ov, 1
   br i1 %ov, label %if.end4, label %return
 
 if.end4:
   tail call void @other(i32* %p) nounwind
   br label %return
 
 return:
   ret void
 }
 
 @a = common global i8 0, align 1
 @d = common global i8 0, align 1
 
 declare void @external_a()
 declare void @external_b()
 declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
 
 define void @test_tail_call(i32* %ptr) nounwind {
-; CHECK-LABEL: test_tail_call:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    addl $1, (%eax)
-; CHECK-NEXT:    setae %al
-; CHECK-NEXT:    addb $1, a
-; CHECK-NEXT:    setb d
-; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    jne .LBB5_2
-; CHECK-NEXT:  # %bb.1: # %then
-; CHECK-NEXT:    jmp external_a # TAILCALL
-; CHECK-NEXT:  .LBB5_2: # %else
-; CHECK-NEXT:    jmp external_b # TAILCALL
+; INCDEC-LABEL: test_tail_call:
+; INCDEC:       # %bb.0: # %entry
+; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; INCDEC-NEXT:    incl (%eax)
+; INCDEC-NEXT:    setne %al
+; INCDEC-NEXT:    incb a
+; INCDEC-NEXT:    sete d
+; INCDEC-NEXT:    testb %al, %al
+; INCDEC-NEXT:    jne .LBB5_2
+; INCDEC-NEXT:  # %bb.1: # %then
+; INCDEC-NEXT:    jmp external_a # TAILCALL
+; INCDEC-NEXT:  .LBB5_2: # %else
+; INCDEC-NEXT:    jmp external_b # TAILCALL
+;
+; ADD-LABEL: test_tail_call:
+; ADD:       # %bb.0: # %entry
+; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; ADD-NEXT:    addl $1, (%eax)
+; ADD-NEXT:    setne %al
+; ADD-NEXT:    addb $1, a
+; ADD-NEXT:    sete d
+; ADD-NEXT:    testb %al, %al
+; ADD-NEXT:    jne .LBB5_2
+; ADD-NEXT:  # %bb.1: # %then
+; ADD-NEXT:    jmp external_a # TAILCALL
+; ADD-NEXT:  .LBB5_2: # %else
+; ADD-NEXT:    jmp external_b # TAILCALL
 entry:
   %val = load i32, i32* %ptr
   %add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1)
   %inc = extractvalue { i32, i1 } %add_ov, 0
   store i32 %inc, i32* %ptr
   %cmp = extractvalue { i32, i1 } %add_ov, 1
   %aval = load volatile i8, i8* @a
   %add_ov2 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %aval, i8 1)

llvm/trunk/test/CodeGen/X86/xaluo.ll

; FAST-NEXT:    retq
   store i64 %val, i64* %res
   ret i1 %obit
 }
 
 ; UADDO reg, 1 | NOT INC
 define zeroext i1 @uaddoinci8(i8 %v1, i8* %res) {
 ; SDAG-LABEL: uaddoinci8:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    addb $1, %dil
-; SDAG-NEXT:    setb %al
+; SDAG-NEXT:    incb %dil
+; SDAG-NEXT:    sete %al
 ; SDAG-NEXT:    movb %dil, (%rsi)
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: uaddoinci8:
 ; FAST:       ## %bb.0:
 ; FAST-NEXT:    addb $1, %dil
 ; FAST-NEXT:    setb %al
 ; FAST-NEXT:    movb %dil, (%rsi)
 ; FAST-NEXT:    andb $1, %al
 ; FAST-NEXT:    movzbl %al, %eax
 ; FAST-NEXT:    retq
   %t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %v1, i8 1)
   %val = extractvalue {i8, i1} %t, 0
   %obit = extractvalue {i8, i1} %t, 1
   store i8 %val, i8* %res
   ret i1 %obit
 }
 
 define zeroext i1 @uaddoinci16(i16 %v1, i16* %res) {
 ; SDAG-LABEL: uaddoinci16:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    addw $1, %di
-; SDAG-NEXT:    setb %al
+; SDAG-NEXT:    incw %di
+; SDAG-NEXT:    sete %al
 ; SDAG-NEXT:    movw %di, (%rsi)
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: uaddoinci16:
 ; FAST:       ## %bb.0:
 ; FAST-NEXT:    addw $1, %di
 ; FAST-NEXT:    setb %al
 ; FAST-NEXT:    movw %di, (%rsi)
 ; FAST-NEXT:    andb $1, %al
 ; FAST-NEXT:    movzbl %al, %eax
 ; FAST-NEXT:    retq
   %t = call {i16, i1} @llvm.uadd.with.overflow.i16(i16 %v1, i16 1)
   %val = extractvalue {i16, i1} %t, 0
   %obit = extractvalue {i16, i1} %t, 1
   store i16 %val, i16* %res
   ret i1 %obit
 }
 
 define zeroext i1 @uaddoinci32(i32 %v1, i32* %res) {
 ; SDAG-LABEL: uaddoinci32:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    addl $1, %edi
-; SDAG-NEXT:    setb %al
+; SDAG-NEXT:    incl %edi
+; SDAG-NEXT:    sete %al
 ; SDAG-NEXT:    movl %edi, (%rsi)
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: uaddoinci32:
 ; FAST:       ## %bb.0:
 ; FAST-NEXT:    addl $1, %edi
 ; FAST-NEXT:    setb %al
 ; FAST-NEXT:    movl %edi, (%rsi)
 ; FAST-NEXT:    andb $1, %al
 ; FAST-NEXT:    movzbl %al, %eax
 ; FAST-NEXT:    retq
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }
 
 define zeroext i1 @uaddoinci64(i64 %v1, i64* %res) {
 ; SDAG-LABEL: uaddoinci64:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    addq $1, %rdi
-; SDAG-NEXT:    setb %al
+; SDAG-NEXT:    incq %rdi
+; SDAG-NEXT:    sete %al
 ; SDAG-NEXT:    movq %rdi, (%rsi)
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: uaddoinci64:
 ; FAST:       ## %bb.0:
 ; FAST-NEXT:    addq $1, %rdi
 ; FAST-NEXT:    setb %al
 ; FAST-NEXT:    movq %rdi, (%rsi)