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Differential D57485

[GlobalISel] Add IRTranslator support for G_FFLOOR
ClosedPublic

Authored by paquette on Jan 30 2019, 4:21 PM.

Details

Reviewers
aemerson
Commits
rG73158e72012c: [GlobalISel] Add IRTranslator support for G_FFLOOR
rL353058: [GlobalISel] Add IRTranslator support for G_FFLOOR
Summary

Follow-up to https://reviews.llvm.org/D57484

Adds G_FFLOOR to translateKnownIntrinsic and update arm64-irtranslator.ll.

Diff Detail

Repository
rL LLVM

Event Timeline

paquette created this revision.Jan 30 2019, 4:21 PM
Herald added subscribers: Petar.Avramovic, volkan, kristof.beyls and 2 others. · View Herald TranscriptJan 30 2019, 4:21 PM
paquette added a parent revision: D57484: [GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR.Jan 30 2019, 4:22 PM
paquette added a child revision: D57486: [GlobalISel][AArch64] Select G_FFLOOR.Jan 30 2019, 4:24 PM
aemerson accepted this revision.Feb 1 2019, 4:05 PM
This revision is now accepted and ready to land.Feb 1 2019, 4:05 PM
Closed by commit rL353058: [GlobalISel] Add IRTranslator support for G_FFLOOR (authored by paquette). · Explain WhyFeb 4 2019, 9:18 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 4 2019, 9:18 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
GlobalISel/
5 lines
test/
CodeGen/
AArch64/
GlobalISel/
8 lines

Diff 185067

llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,071 Lines • ▼ Show 20 Linesbool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
} }
case Intrinsic::invariant_end: case Intrinsic::invariant_end:
return true; return true;
case Intrinsic::ceil: case Intrinsic::ceil:
MIRBuilder.buildInstr(TargetOpcode::G_FCEIL) MIRBuilder.buildInstr(TargetOpcode::G_FCEIL)
.addDef(getOrCreateVReg(CI)) .addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0))); .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true; return true;
case Intrinsic::floor:
MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::cos: case Intrinsic::cos:
MIRBuilder.buildInstr(TargetOpcode::G_FCOS) MIRBuilder.buildInstr(TargetOpcode::G_FCOS)
.addDef(getOrCreateVReg(CI)) .addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0))); .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true; return true;
case Intrinsic::sin: case Intrinsic::sin:
MIRBuilder.buildInstr(TargetOpcode::G_FSIN) MIRBuilder.buildInstr(TargetOpcode::G_FSIN)
.addDef(getOrCreateVReg(CI)) .addDef(getOrCreateVReg(CI))
▲ Show 20 Lines • Show All 842 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Show First 20 Lines • Show All 2,318 Lines • ▼ Show 20 Lines
declare float @llvm.sqrt.f32(float) declare float @llvm.sqrt.f32(float)
define float @test_sqrt_f32(float %x) { define float @test_sqrt_f32(float %x) {
; CHECK-LABEL: name: test_sqrt_f32 ; CHECK-LABEL: name: test_sqrt_f32
; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}} ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
%y = call float @llvm.sqrt.f32(float %x) %y = call float @llvm.sqrt.f32(float %x)
ret float %y ret float %y
} }
declare float @llvm.floor.f32(float)
define float @test_floor_f32(float %x) {
; CHECK-LABEL: name: test_floor_f32
; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
%y = call float @llvm.floor.f32(float %x)
ret float %y
}
; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32 ; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64) ; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64)
define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) { define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) {
%arst = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) %arst = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr)
ret void ret void
} }
declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32*) #3 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32*) #3