[GlobalISel][AArch64] Select G_FABS

[paquette]

Summary

This adds instruction selection support for G_FABS in AArch64. It also updates the existing basic FP tests, adds a selection test for G_FABS.

[aemerson]

LGTM.

[paquette]

Committed in r352684

include/llvm/Target/GlobalISel/SelectionDAGCompat.td

 def : GINodeEquiv<G_CTTZ, cttz>;
 def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
 def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
 def : GINodeEquiv<G_CTPOP, ctpop>;
 def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
 def : GINodeEquiv<G_FCEIL, fceil>;
 def : GINodeEquiv<G_FCOS, fcos>;
 def : GINodeEquiv<G_FSIN, fsin>;
+def : GINodeEquiv<G_FABS, fabs>;
 
 // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
 // complications that tablegen must take care of. For example, Predicates such
 // as isSignExtLoad require that this is not a perfect 1:1 mapping since a
 // sign-extending load is (G_SEXTLOAD x) in GlobalISel. Additionally,
 // G_LOAD handles both atomic and non-atomic loads where as SelectionDAG had
 // separate nodes for them. This GINodeEquiv maps the non-atomic loads to
 // G_LOAD with a non-atomic MachineMemOperand.

lib/Target/AArch64/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   getActionDefinitionsBuilder({G_UADDE, G_USUBE, G_SADDO, G_SSUBO})
       .legalFor({{s32, s1}, {s64, s1}});
 
   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV, G_FNEG})
     .legalFor({s32, s64, v2s64, v4s32, v2s32});
 
   getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
 
-  getActionDefinitionsBuilder(G_FCEIL)
+  getActionDefinitionsBuilder({G_FCEIL, G_FABS})
       // If we don't have full FP16 support, then scalarize the elements of
       // vectors containing fp16 types.
       .fewerElementsIf(
           [=, &ST](const LegalityQuery &Query) {
             const auto &Ty = Query.Types[0];
             return Ty.isVector() && Ty.getElementType() == s16 &&
                    !ST.hasFullFP16();
           },

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
   case TargetOpcode::G_FPEXT:
   case TargetOpcode::G_FPTRUNC:
   case TargetOpcode::G_FCEIL:
   case TargetOpcode::G_FNEG:
   case TargetOpcode::G_FCOS:
   case TargetOpcode::G_FSIN:
   case TargetOpcode::G_FLOG10:
   case TargetOpcode::G_FLOG:
+  case TargetOpcode::G_FABS:
     return true;
   }
   return false;
 }
 
 const RegisterBankInfo::InstructionMapping &
 AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
     const MachineInstr &MI) const {

test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 #
 # DEBUG-NEXT: G_SITOFP (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_UITOFP (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_FABS (opcode {{[0-9]+}}): 1 type index
-# DEBUG:      .. type index coverage check SKIPPED: no rules defined
+# DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected
 #
 # DEBUG-NEXT: G_GEP (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_PTR_MASK (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices

test/CodeGen/AArch64/GlobalISel/select-fabs.mir

+# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
+# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
+# RUN: | FileCheck %s
+...
+---
+name:            fabs_float
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_float
+    ; CHECK: %{{[0-9]+}}:fpr32 = FABSSr %{{[0-9]+}}
+    liveins: $s0
+    %0:fpr(s32) = COPY $s0
+    %1:fpr(s32) = G_FABS %0
+    $s0 = COPY %1(s32)
+
+...
+---
+name:            fabs_double
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_double
+    ; CHECK: %{{[0-9]+}}:fpr64 = FABSDr %{{[0-9]+}}
+    liveins: $d0
+    %0:fpr(s64) = COPY $d0
+    %1:fpr(s64) = G_FABS %0
+    $d0 = COPY %1(s64)
+
+...
+---
+name:            fabs_v2f32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_v2f32
+    ; CHECK: %{{[0-9]+}}:fpr64 = FABSv2f32 %{{[0-9]+}}
+    liveins: $d0
+    %0:fpr(<2 x s32>) = COPY $d0
+    %1:fpr(<2 x s32>) = G_FABS %0
+    $d0 = COPY %1(<2 x s32>)
+
+...
+---
+name:            fabs_v4f32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_v4f32
+    ; CHECK: %{{[0-9]+}}:fpr128 = FABSv4f32 %{{[0-9]+}}
+    liveins: $q0
+    %0:fpr(<4 x s32>) = COPY $q0
+    %1:fpr(<4 x s32>) = G_FABS %0
+    $q0 = COPY %1(<4 x s32>)
+
+...
+---
+name:            fabs_v2f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_v2f64
+    ; CHECK: %{{[0-9]+}}:fpr128 = FABSv2f64 %{{[0-9]+}}
+    liveins: $q0
+    %0:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s64>) = G_FABS %0
+    $q0 = COPY %1(<2 x s64>)
+
+...
+---
+name:            fabs_v4f16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_v4f16
+    ; CHECK: %{{[0-9]+}}:fpr64 = FABSv4f16 %{{[0-9]+}}
+    liveins: $d0
+    %0:fpr(<4 x s16>) = COPY $d0
+    %1:fpr(<4 x s16>) = G_FABS %0
+    $d0 = COPY %1(<4 x s16>)
+
+...
+---
+name:            fabs_v8f16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            fabs_v8f16
+    ; CHECK: %{{[0-9]+}}:fpr128 = FABSv8f16 %{{[0-9]+}}
+    liveins: $q0
+    %0:fpr(<8 x s16>) = COPY $q0
+    %1:fpr(<8 x s16>) = G_FABS %0
+    $q0 = COPY %1(<8 x s16>)
+
+...

test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

 define %v4f16 @test_v4f16.fma(%v4f16 %a, %v4f16 %b, %v4f16 %c) {
   ; CHECK-LABEL:          test_v4f16.fma:
   ; CHECK-NOFP16-COUNT-4: fmadd s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           fmla.4h
   %1 = call %v4f16 @llvm.fma.v4f16(%v4f16 %a, %v4f16 %b, %v4f16 %c)
   ret %v4f16 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v4f16.fabs
 define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
   ; CHECK-LABEL:          test_v4f16.fabs:
   ; CHECK-NOFP16-COUNT-4: fabs s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           fabs.4h
   ; CHECK-FP16-NEXT:      ret
+
+  ; GISEL-LABEL:          test_v4f16.fabs:
+  ; GISEL-NOFP16-COUNT-4: fabs s{{[0-9]+}}, s{{[0-9]+}}
+  ; GISEL-FP16-NOT:       fcvt
+  ; GISEL-FP16:           fabs.4h
+  ; GISEL-FP16-NEXT:      ret
   %1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
   ret %v4f16 %1
 }
 define %v4f16 @test_v4f16.floor(%v4f16 %a) {
   ; CHECK-LABEL:          test_v4f16.floor:
   ; CHECK-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           frintm.4h

 define %v8f16 @test_v8f16.fma(%v8f16 %a, %v8f16 %b, %v8f16 %c) {
   ; CHECK-LABEL:          test_v8f16.fma:
   ; CHECK-NOFP16-COUNT-8: fmadd s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           fmla.8h
   %1 = call %v8f16 @llvm.fma.v8f16(%v8f16 %a, %v8f16 %b, %v8f16 %c)
   ret %v8f16 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v8f16.fabs
 define %v8f16 @test_v8f16.fabs(%v8f16 %a) {
   ; CHECK-LABEL:          test_v8f16.fabs:
   ; CHECK-NOFP16-COUNT-8: fabs s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           fabs.8h
   ; CHECK-FP16-NEXT:      ret
+
+  ; GISEL-LABEL:          test_v8f16.fabs:
+  ; GISEL-NOFP16-COUNT-8: fabs s{{[0-9]+}}, s{{[0-9]+}}
+  ; GISEL-FP16-NOT:       fcvt
+  ; GISEL-FP16:           fabs.8h
+  ; GISEL-FP16-NEXT:      ret
   %1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a)
   ret %v8f16 %1
 }
 define %v8f16 @test_v8f16.floor(%v8f16 %a) {
   ; CHECK-LABEL:          test_v8f16.floor:
   ; CHECK-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           frintm.8h
define %v2f32 @test_v2f32.log2(%v2f32 %a) {
   ret %v2f32 %1
 }
 ; CHECK-LABEL: test_v2f32.fma:
 define %v2f32 @test_v2f32.fma(%v2f32 %a, %v2f32 %b, %v2f32 %c) {
   ; CHECK: fmla.2s
   %1 = call %v2f32 @llvm.fma.v2f32(%v2f32 %a, %v2f32 %b, %v2f32 %c)
   ret %v2f32 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v2f32.fabs
 ; CHECK-LABEL: test_v2f32.fabs:
+; GISEL-LABEL: test_v2f32.fabs:
 define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
   ; CHECK: fabs.2s
+  ; GISEL: fabs.2s
   %1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
 ; CHECK-LABEL: test_v2f32.floor:
 define %v2f32 @test_v2f32.floor(%v2f32 %a) {
   ; CHECK: frintm.2s
   %1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
   ret %v2f32 %1
define %v4f32 @test_v4f32.log2(%v4f32 %a) {
   ret %v4f32 %1
 }
 ; CHECK: test_v4f32.fma:
 define %v4f32 @test_v4f32.fma(%v4f32 %a, %v4f32 %b, %v4f32 %c) {
   ; CHECK: fma
   %1 = call %v4f32 @llvm.fma.v4f32(%v4f32 %a, %v4f32 %b, %v4f32 %c)
   ret %v4f32 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v4f32.fabs
 ; CHECK: test_v4f32.fabs:
+; GISEL: test_v4f32.fabs:
 define %v4f32 @test_v4f32.fabs(%v4f32 %a) {
   ; CHECK: fabs
+  ; GISEL: fabs
   %1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 ; CHECK: test_v4f32.floor:
 define %v4f32 @test_v4f32.floor(%v4f32 %a) {
   ; CHECK: frintm.4s
   %1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
   ret %v4f32 %1
define %v2f64 @test_v2f64.log2(%v2f64 %a) {
   ret %v2f64 %1
 }
 ; CHECK: test_v2f64.fma:
 define %v2f64 @test_v2f64.fma(%v2f64 %a, %v2f64 %b, %v2f64 %c) {
   ; CHECK: fma
   %1 = call %v2f64 @llvm.fma.v2f64(%v2f64 %a, %v2f64 %b, %v2f64 %c)
   ret %v2f64 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v2f64.fabs
 ; CHECK: test_v2f64.fabs:
+; GISEL: test_v2f64.fabs:
 define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
   ; CHECK: fabs
+  ; GISEL: fabs
   %1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }
 ; CHECK: test_v2f64.floor:
 define %v2f64 @test_v2f64.floor(%v2f64 %a) {
   ; CHECK: frintm.2d
   %1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a)
   ret %v2f64 %1

test/CodeGen/AArch64/f16-instructions.ll

 ; CHECK-CVT-NEXT: fabs s0, s0
 ; CHECK-CVT-NEXT: fcvt h0, s0
 ; CHECK-CVT-NEXT: ret
 
 ; CHECK-FP16-LABEL: test_fabs:
 ; CHECK-FP16-NEXT: fabs h0, h0
 ; CHECK-FP16-NEXT: ret
 
+; FALLBACK-NOT: remark:{{.*}}test_fabs
+; FALLBACK-FP16-NOT: remark:{{.*}}test_fabs
+
+; GISEL-CVT-LABEL: test_fabs:
+; GISEL-CVT-NEXT: fcvt s0, h0
+; GISEL-CVT-NEXT: fabs s0, s0
+; GISEL-CVT-NEXT: fcvt h0, s0
+; GISEL-CVT-NEXT: ret
+
+; GISEL-FP16-LABEL: test_fabs:
+; GISEL-FP16-NEXT: fabs h0, h0
+; GISEL-FP16-NEXT: ret
+
 define half @test_fabs(half %a) #0 {
   %r = call half @llvm.fabs.f16(half %a)
   ret half %r
 }
 
 ; CHECK-CVT-LABEL: test_minnum:
 ; CHECK-CVT-NEXT: fcvt s1, h1
 ; CHECK-CVT-NEXT: fcvt s0, h0