Page MenuHomePhabricator

[X86] Improve use of SHLD/SHRD
Needs ReviewPublic

Authored by deadalnix on Tue, Jan 29, 7:43 AM.

Details

Summary

This extends the variety of pattern that can generate a SHLD instead of using two shifts.

This fixes a regression that would be introduced by D57367 or D33587

Diff Detail

Event Timeline

deadalnix created this revision.Tue, Jan 29, 7:43 AM
RKSimon added inline comments.Tue, Jan 29, 8:02 AM
lib/Target/X86/X86ISelLowering.cpp
37054

Maybe use DAG.GetDemandedBits ?

deadalnix marked 2 inline comments as done.Tue, Jan 29, 5:24 PM
deadalnix added inline comments.
lib/Target/X86/X86ISelLowering.cpp
37020

The operation is similar to what's done here.

37054

It's not obvious to me that it would work. The and opcode itself uses it, so there is no need to redo it here. We also need to know if masking took place to know what we can accept as LHS for the sub opcode.

craig.topper added inline comments.Tue, Jan 29, 7:40 PM
lib/Target/X86/X86ISelLowering.cpp
37054

I know this code (Bits - 1) check is used in other places earlier in this function, but is that valid for i16 SHLD/SHRD? SHLD/SHRD hardware mask shift amount to 5 bits on i16/i32 and 6 bits on i64.

We might be better off just working on getting this code moved into DAGCombine (https://bugs.llvm.org/show_bug.cgi?id=40081) and use generic funnel shifts.

deadalnix marked an inline comment as done.Thu, Jan 31, 5:23 PM

@RKSimon That sound reasonable. The main motivation for this patch is to fix a regression introduced by D57367 , so would that be possible to get at least a concept ack on it ?

lib/Target/X86/X86ISelLowering.cpp
37054

I do not know if this is valid for i16. If that isn't, this code is bogous already. Would you have a test case I can rely on to do this ?

Herald added a project: Restricted Project. · View Herald TranscriptThu, Jan 31, 5:23 PM
craig.topper added inline comments.Thu, Feb 7, 3:40 PM
lib/Target/X86/X86ISelLowering.cpp
37054

@RKSimon what are you thoughts on the existing uses of (Bits - 1) in this function for the i16 case? Those seem wrong to me.

RKSimon added inline comments.Fri, Feb 8, 1:28 AM
lib/Target/X86/X86ISelLowering.cpp
37054

Yes I think its wrong - we're most likely being saved by the fact that its so tricky to create i16 double shifts from code (PR35155). As I said I'd much prefer to kill all this code and move it to FSHL/FSHR in DAGCombine (PR40081) - I'll take a look.

RKSimon added inline comments.Sat, Feb 9, 12:52 PM
lib/Target/X86/X86ISelLowering.cpp
37054

Unravelling all of this code is proving trickier than I hoped due to various custom/legalization issues. I've committed rL353626 which folds to FSHL/FSHR and a fix for the i16 issue.

@deadalnix Please can you rebase this?