GlobalISel: Fix out of bounds crashes in verifier

[arsenm]

r351769

lib/CodeGen/MachineVerifier.cpp

if (MI->isDebugInstr()) {
         report("Missing slot index", MI);
     }
   }
 
   if (isPreISelGenericOpcode(MCID.getOpcode())) {
     if (isFunctionSelected)
       report("Unexpected generic instruction in a Selected function", MI);
 
+    unsigned NumOps = MI->getNumOperands();
+
     // Check types.
     SmallVector<LLT, 4> Types;
-    for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
+    for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
+         I != E; ++I) {
       if (!MCID.OpInfo[I].isGenericType())
         continue;
       // Generic instructions specify type equality constraints between some of
       // their operands. Make sure these are consistent.
       size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
       Types.resize(std::max(TypeIdx + 1, Types.size()));
 
       const MachineOperand *MO = &MI->getOperand(I);
if (isPreISelGenericOpcode(MCID.getOpcode())) {
     }
 
     // Generic opcodes must not have physical register operands.
     for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
       const MachineOperand *MO = &MI->getOperand(I);
       if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg()))
         report("Generic instruction cannot have physical register", MO, I);
     }
+
+    // Avoid out of bounds in checks below. This was already reported earlier.
+    if (MI->getNumOperands() < MCID.getNumOperands())
+      return;
   }
 
   StringRef ErrorInfo;
   if (!TII->verifyInstruction(*MI, ErrorInfo))
     report(ErrorInfo.data(), MI);
 
   // Verify properties of various specific instruction types
   switch(MI->getOpcode()) {
void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   case TargetOpcode::G_FPEXT:
   case TargetOpcode::G_FPTRUNC: {
     // Number of operands and presense of types is already checked (and
     // reported in case of any issues), so no need to report them again. As
     // we're trying to report as many issues as possible at once, however, the
     // instructions aren't guaranteed to have the right number of operands or
     // types attached to them at this point
     assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
-    if (MI->getNumOperands() < MCID.getNumOperands())
-      break;
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
     if (!DstTy.isValid() || !SrcTy.isValid())
       break;
 
     LLT DstElTy = DstTy.isVector() ? DstTy.getElementType() : DstTy;
     LLT SrcElTy = SrcTy.isVector() ? SrcTy.getElementType() : SrcTy;
     if (DstElTy.isPointer() || SrcElTy.isPointer())

test/Verifier/test_g_add.mir

+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_add
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+
+    ; CHECK: Bad machine code: Too few operands
+    %2:_(s32) = G_ADD
+
+    ; CHECK: Bad machine code: Too few operands
+    %3:_(s32) = G_ADD %0
+    %4:_(s32) = G_ADD %0, %1
+
+    ; CHECK: Bad machine code: Too few operands
+    ; CHECK: Bad machine code: Explicit definition marked as use
+    G_ADD %0, %1
+
+...

test/Verifier/test_g_constant.mir

 #RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: global-isel, aarch64-registered-target
 
 ---
-name:            test_constant_vector
+name:            test_constant
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 liveins:
 body:             |
   bb.0:
     ; CHECK: Bad machine code: Instruction cannot use a vector result type
     %0:_(<2 x s32>) = G_CONSTANT i32 0
+
+    ; CHECK: Bad machine code: Too few operands
+    %1:_(s32) = G_CONSTANT
 ...

test/Verifier/test_g_trunc.mir

+# RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_trunc
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Too few operands
+    %0:_(s32) = G_TRUNC
+
+    %1:_(s64) = G_IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: Too few operands
+    ; CHECK: Bad machine code: Explicit definition marked as use
+    G_TRUNC %1
+
+...