[WebAssembly] Standardize order of SIMD bitselect arguments

[tlively]

Summary

For some reason the backend assumed that the condition mask would be
the first argument to the LLVM intrinsic, but everywhere else the
condition mask is the third argument.

[aheejin]

Any affected tests?

[tlively]

Update tests

[tlively]

In D56412#1348846, @aheejin wrote:

Any affected tests?

Yep, my bad. Fixed now.

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 } // isCommutable = 1
 
 // Bitwise select: v128.bitselect
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
   defm BITSELECT_#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
            [(set (vec_t V128:$dst),
              (vec_t (int_wasm_bitselect
-               (vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2)
+               (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
              ))
            )],
            "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
 
 // Bitselect is equivalent to (c & v1) | (~c & v2)
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
   def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
               (and (vnot V128:$c), (vec_t V128:$v2)))),