Test case for patch D52002

[ayonam]

Summary

This is a test case for the patch D52002. It checks whether a compare followed by a branch is being generated or not if the default is unreachable. The patch D52002 implements the removal of this compare and branch when the default case is unreachable for a switch statement.

[hans]

Looks promising. Please make the suggested changes, and please move this patch into D52002. The functionality change and the test should be in the same patch.

test/CodeGen/AArch64/switch-unreachable-default.ll

1

I think for a simple case like this, it should be possible to write the assertions manually.

10

No need for dso_local, nocapture, readonly, local_unnamed_addr, or the attributes in #0. Please remove them to simplify the test.

13

Having these checks before the function starts doesn't look right.

I think the test should be something like

CHECK-LABEL: fn:
CHECK-NOT: sub
CHECK-NOT: cmp
CHECK: load jump target
CHECK: branch to jump target

41

I'd suggest just taking the switch argument directly as an argument of the function. I.e. make %0 an i8 instead of i32* above, and switch on that directly. Then there's no need to load, trunc, etc, and that will simplify the test.

42

I prefer to use explicit names for the basic blocks, i.e. instead fo %4, call it %default maybe, and then %case0, %case1, etc. for the case blocks.

[efriedma]

llvm-commits is not CC'ed on this revision; llvm-commits is the official record for all reviews, so any patch posted without CC'ing llvm-commits essentially doesn't exist. It looks like you're going to abandon this anyway, but please be more careful in the future.

[ayonam]

In D55901#1337308, @hans wrote:

Looks promising. Please make the suggested changes, and please move this patch into D52002. The functionality change and the test should be in the same patch.

Done.

[ayonam]

In D55901#1337708, @efriedma wrote:

llvm-commits is not CC'ed on this revision; llvm-commits is the official record for all reviews, so any patch posted without CC'ing llvm-commits essentially doesn't exist. It looks like you're going to abandon this anyway, but please be more careful in the future.

Thanks Eli for bringing this to my notice. I wasn't aware of this aspect. I thought, the reviews here automatically become the record and I just need to quote the review ID while committing the code. Anyway, as you said, I'll be abandoning this patch and have already moved it to 52002. Thanks again.

[ayonam]

This test case has been subsumed in D52002

test/CodeGen/AArch64/switch-unreachable-default.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -o - %s | FileCheck %s
+
+; Test that the output in the presence of an unreachable default does not have
+; a compare and branch at the top of the switch to handle the default case.
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define dso_local void @fn(i32* nocapture readonly) local_unnamed_addr #0 {
+; CHECK-NOT:    sub
+; CHECK-NOT:    cmp
+; CHECK-NOT:    b.hi
+; CHECK-LABEL: fn:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w0, [x0]
+; CHECK-NEXT:    adrp x9, .LJTI0_0
+; CHECK-NEXT:    add x9, x9, :lo12:.LJTI0_0
+; CHECK-NEXT:    and x8, x0, #0xf
+; CHECK-NEXT:    ldr x8, [x9, x8, lsl #3]
+; CHECK-NEXT:    br x8
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_00
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_01
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_02
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_03
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_04
+; CHECK-NEXT:  .LBB0_6:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    b handle_case_05
+  %2 = load i32, i32* %0, align 4
+  %3 = trunc i32 %2 to i4
+  switch i4 %3, label %4 [
+    i4 0, label %5
+    i4 1, label %6
+    i4 2, label %7
+    i4 3, label %8
+    i4 4, label %9
+    i4 5, label %10
+  ]
+
+; <label>:4:                                      ; preds = %1
+  unreachable
+
+; <label>:5:                                      ; preds = %1
+  tail call void @handle_case_00(i32 %2) #2
+  br label %11
+
+; <label>:6:                                      ; preds = %1
+  tail call void @handle_case_01(i32 %2) #2
+  br label %11
+
+; <label>:7:                                      ; preds = %1
+  tail call void @handle_case_02(i32 %2) #2
+  br label %11
+
+; <label>:8:                                      ; preds = %1
+  tail call void @handle_case_03(i32 %2) #2
+  br label %11
+
+; <label>:9:                                      ; preds = %1
+  tail call void @handle_case_04(i32 %2) #2
+  br label %11
+
+; <label>:10:                                     ; preds = %1
+  tail call void @handle_case_05(i32 %2) #2
+  br label %11
+
+; <label>:11:                                     ; preds = %10, %9, %8, %7, %6, %5
+  ret void
+}
+
+declare dso_local void @handle_case_00(i32) local_unnamed_addr #1
+
+declare dso_local void @handle_case_01(i32) local_unnamed_addr #1
+
+declare dso_local void @handle_case_02(i32) local_unnamed_addr #1
+
+declare dso_local void @handle_case_03(i32) local_unnamed_addr #1
+
+declare dso_local void @handle_case_04(i32) local_unnamed_addr #1
+
+declare dso_local void @handle_case_05(i32) local_unnamed_addr #1
+