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AMDGPU/GlobalISel: Introduce vcc reg bank
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Authored by arsenm on Dec 17 2018, 2:27 AM.

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Summary

I'm not entirely sure this is the correct thing
to do with the global isel philosophy, but I think
this is necessary to handle how differently SGPRs
are used normally vs. from a condition.

For example, it makes sense to allow a copy
from a VGPR to an SGPR, but it makes no sense
to allow a copy from VGPRs to SGPRs used as
select mask.

This avoids regbankselecting strange code with
a truncate feeding directly into a condition field.
Now a copy is forced from sgpr(s1) to vcc, which is
more sensible to handle.

Some of these issues could probably avoided with making enough
operations resulting in i1 illegal. I think we can't avoid
this register bank for legality.

For example, an i1 and where one source is from a truncate, and
one source is a compare needs some kind of copy inserted to
make sure both are in condition registers.

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arsenm created this revision.Dec 17 2018, 2:27 AM

Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 17 2018, 2:27 AM

Rebase and include some examples that I think show this is needed

arsenm added parent revisions: D55880: AMDGPU: Make i1/i64/v2i32 and/or/xor legal, D55871: AMDGPU/GlobalISel: Disallow VGPR->SCC copies.Dec 19 2018, 12:28 AM

LGTM.

This revision is now accepted and ready to land.Dec 19 2018, 1:50 PM

r350611

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

AMDGPUGenRegisterBankInfo.def

57 lines

AMDGPURegisterBankInfo.cpp

43 lines

AMDGPURegisterBanks.td

5 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

regbankselect-amdgcn-wqm-vote.mir

5 lines

regbankselect-and.mir

18 lines

regbankselect-brcond.mir

13 lines

regbankselect-fcmp.mir

8 lines

regbankselect-icmp.mir

6 lines

regbankselect-sadde.mir

25 lines

regbankselect-saddo.mir

6 lines

regbankselect-select.mir

16 lines

regbankselect-ssube.mir

25 lines

regbankselect-ssubo.mir

6 lines

regbankselect-uadde.mir

25 lines

regbankselect-uaddo.mir

6 lines

regbankselect-usube.mir

25 lines

regbankselect-usubo.mir

6 lines

Diff 178841

lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

	Show All 10 Lines
	/// \todo This should be generated by TableGen.			/// \todo This should be generated by TableGen.
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	namespace llvm {			namespace llvm {
	namespace AMDGPU {			namespace AMDGPU {

	enum PartialMappingIdx {			enum PartialMappingIdx {
	None = - 1,			None = - 1,
	PM_SGPR1 = 1,			PM_SGPR1 = 2,
	PM_SGPR16 = 5,			PM_SGPR16 = 6,
	PM_SGPR32 = 6,			PM_SGPR32 = 7,
	PM_SGPR64 = 7,			PM_SGPR64 = 8,
	PM_SGPR128 = 8,			PM_SGPR128 = 9,
	PM_SGPR256 = 9,			PM_SGPR256 = 10,
	PM_SGPR512 = 10,			PM_SGPR512 = 11,
	PM_VGPR1 = 11,			PM_VGPR1 = 12,
	PM_VGPR16 = 15,			PM_VGPR16 = 16,
	PM_VGPR32 = 16,			PM_VGPR32 = 17,
	PM_VGPR64 = 17,			PM_VGPR64 = 18,
	PM_VGPR128 = 18,			PM_VGPR128 = 19,
	PM_VGPR256 = 19,			PM_VGPR256 = 20,
	PM_VGPR512 = 20,			PM_VGPR512 = 21,
	PM_SGPR96 = 21,			PM_SGPR96 = 22,
	PM_VGPR96 = 22			PM_VGPR96 = 23
	};			};

	const RegisterBankInfo::PartialMapping PartMappings[] {			const RegisterBankInfo::PartialMapping PartMappings[] {
	// StartIdx, Length, RegBank			// StartIdx, Length, RegBank
	{0, 1, SCCRegBank},			{0, 1, SCCRegBank},
				{0, 1, VCCRegBank},

	{0, 1, SGPRRegBank}, // SGPR begin			{0, 1, SGPRRegBank}, // SGPR begin
	{0, 16, SGPRRegBank},			{0, 16, SGPRRegBank},
	{0, 32, SGPRRegBank},			{0, 32, SGPRRegBank},
	{0, 64, SGPRRegBank},			{0, 64, SGPRRegBank},
	{0, 128, SGPRRegBank},			{0, 128, SGPRRegBank},
	{0, 256, SGPRRegBank},			{0, 256, SGPRRegBank},
	{0, 512, SGPRRegBank},			{0, 512, SGPRRegBank},

	{0, 1, VGPRRegBank}, // VGPR begin			{0, 1, VGPRRegBank}, // VGPR begin
	{0, 16, VGPRRegBank},			{0, 16, VGPRRegBank},
	{0, 32, VGPRRegBank},			{0, 32, VGPRRegBank},
	{0, 64, VGPRRegBank},			{0, 64, VGPRRegBank},
	{0, 128, VGPRRegBank},			{0, 128, VGPRRegBank},
	{0, 256, VGPRRegBank},			{0, 256, VGPRRegBank},
	{0, 512, VGPRRegBank},			{0, 512, VGPRRegBank},
	{0, 96, SGPRRegBank},			{0, 96, SGPRRegBank},
	{0, 96, VGPRRegBank},			{0, 96, VGPRRegBank},
	};			};

	const RegisterBankInfo::ValueMapping ValMappings[] {			const RegisterBankInfo::ValueMapping ValMappings[] {
	// SCC			// SCC
	{&PartMappings[0], 1},			{&PartMappings[0], 1},

	// SGPRs			// VCC
	{&PartMappings[1], 1},			{&PartMappings[1], 1},

				// SGPRs
				{&PartMappings[2], 1},
	{nullptr, 0}, // Illegal power of 2 sizes			{nullptr, 0}, // Illegal power of 2 sizes
	{nullptr, 0},			{nullptr, 0},
	{nullptr, 0},			{nullptr, 0},
	{&PartMappings[2], 1},
	{&PartMappings[3], 1},			{&PartMappings[3], 1},
	{&PartMappings[4], 1},			{&PartMappings[4], 1},
	{&PartMappings[5], 1},			{&PartMappings[5], 1},
	{&PartMappings[6], 1},			{&PartMappings[6], 1},
	{&PartMappings[7], 1},			{&PartMappings[7], 1},
				{&PartMappings[8], 1},

	// VGPRs			// VGPRs
	{&PartMappings[8], 1},			{&PartMappings[9], 1},
	{nullptr, 0},			{nullptr, 0},
	{nullptr, 0},			{nullptr, 0},
	{nullptr, 0},			{nullptr, 0},
	{&PartMappings[9], 1},
	{&PartMappings[10], 1},			{&PartMappings[10], 1},
	{&PartMappings[11], 1},			{&PartMappings[11], 1},
	{&PartMappings[12], 1},			{&PartMappings[12], 1},
	{&PartMappings[13], 1},			{&PartMappings[13], 1},
	{&PartMappings[14], 1},			{&PartMappings[14], 1},
	{&PartMappings[15], 1},			{&PartMappings[15], 1},
	{&PartMappings[16], 1}			{&PartMappings[16], 1},
				{&PartMappings[17], 1}
	};			};

	enum ValueMappingIdx {			enum ValueMappingIdx {
	SCCStartIdx = 0,			SCCStartIdx = 0,
	SGPRStartIdx = 1,			SGPRStartIdx = 2,
	VGPRStartIdx = 11			VGPRStartIdx = 12
	};			};

	const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,			const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
	unsigned Size) {			unsigned Size) {
	unsigned Idx;			unsigned Idx;
	switch (Size) {			switch (Size) {
	case 1:			case 1:
	if (BankID == AMDGPU::SCCRegBankID)			if (BankID == AMDGPU::SCCRegBankID)
	return &ValMappings[0];			return &ValMappings[0];
				if (BankID == AMDGPU::VCCRegBankID)
				return &ValMappings[1];

				// 1-bit values not from a compare etc.
	Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;			Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
	break;			break;
	case 96:			case 96:
				assert(BankID != AMDGPU::VCCRegBankID);
	Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;			Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
	break;			break;
	default:			default:
				assert(BankID != AMDGPU::VCCRegBankID);
	Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;			Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
	Idx += Log2_32_Ceil(Size);			Idx += Log2_32_Ceil(Size);
	break;			break;
	}			}

	assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));			assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
	assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());			assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());

	return &ValMappings[Idx];			return &ValMappings[Idx];
	}			}

	} // End AMDGPU namespace.			} // End AMDGPU namespace.
	} // End llvm namespace.			} // End llvm namespace.

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines	static bool isConstant(const MachineOperand &MO, int64_t &C) {
return false;		return false;
}		}

unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,		unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
const RegisterBank &Src,		const RegisterBank &Src,
unsigned Size) const {		unsigned Size) const {
if (Dst.getID() == AMDGPU::SGPRRegBankID &&		if (Dst.getID() == AMDGPU::SGPRRegBankID &&
Src.getID() == AMDGPU::VGPRRegBankID) {		Src.getID() == AMDGPU::VGPRRegBankID) {
// For boolean values, we can do a v_cmp to "copy" a VGPR to VCC.
if (Size == 1)
return 1;

return std::numeric_limits<unsigned>::max();		return std::numeric_limits<unsigned>::max();
}		}

// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by		// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
// the valu.		// the valu.
if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&		if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
(Src.getID() == AMDGPU::SGPRRegBankID \|\|		(Src.getID() == AMDGPU::SGPRRegBankID \|\|
Src.getID() == AMDGPU::VGPRRegBankID))		Src.getID() == AMDGPU::VGPRRegBankID \|\|
		Src.getID() == AMDGPU::VCCRegBankID))
return std::numeric_limits<unsigned>::max();		return std::numeric_limits<unsigned>::max();

		if ((Dst.getID() == AMDGPU::VCCRegBankID &&
		Src.getID() == AMDGPU::SGPRRegBankID) \|\|
		(Dst.getID() == AMDGPU::SGPRRegBankID &&
		Src.getID() == AMDGPU::VCCRegBankID))
		return 0;

return RegisterBankInfo::copyCost(Dst, Src, Size);		return RegisterBankInfo::copyCost(Dst, Src, Size);
}		}

const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(		const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {		const TargetRegisterClass &RC) const {

if (TRI->isSGPRClass(&RC))		if (TRI->isSGPRClass(&RC))
return getRegBank(AMDGPU::SGPRRegBankID);		return getRegBank(AMDGPU::SGPRRegBankID);
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines	const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
nullptr, // Predicate operand.		nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&SSMapping);		AltMappings.push_back(&SSMapping);

const InstructionMapping &SVMapping = getInstructionMapping(2, 1,		const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
nullptr, // Predicate operand.		nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&SVMapping);		AltMappings.push_back(&SVMapping);

const InstructionMapping &VSMapping = getInstructionMapping(3, 1,		const InstructionMapping &VSMapping = getInstructionMapping(3, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
nullptr, // Predicate operand.		nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&VSMapping);		AltMappings.push_back(&VSMapping);

const InstructionMapping &VVMapping = getInstructionMapping(4, 1,		const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
nullptr, // Predicate operand.		nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&VVMapping);		AltMappings.push_back(&VVMapping);

return AltMappings;		return AltMappings;
}		}
case TargetOpcode::G_SELECT: {		case TargetOpcode::G_SELECT: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);		unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,		const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&SSMapping);		AltMappings.push_back(&SSMapping);

const InstructionMapping &SVMapping = getInstructionMapping(2, 1,		const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&SVMapping);		AltMappings.push_back(&SVMapping);

const InstructionMapping &VSMapping = getInstructionMapping(2, 1,		const InstructionMapping &VSMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&VSMapping);		AltMappings.push_back(&VSMapping);

const InstructionMapping &VVMapping = getInstructionMapping(2, 1,		const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
AltMappings.push_back(&VVMapping);		AltMappings.push_back(&VVMapping);

return AltMappings;		return AltMappings;
}		}
case TargetOpcode::G_UADDE:		case TargetOpcode::G_UADDE:
Show All 9 Lines	const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),		AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),
5); // Num Operands		5); // Num Operands
AltMappings.push_back(&SSMapping);		AltMappings.push_back(&SSMapping);


const InstructionMapping &VVMapping = getInstructionMapping(1, 1,		const InstructionMapping &VVMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}),		AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1)}),
5); // Num Operands		5); // Num Operands
AltMappings.push_back(&VVMapping);		AltMappings.push_back(&VVMapping);
return AltMappings;		return AltMappings;
}		}
case AMDGPU::G_BRCOND: {		case AMDGPU::G_BRCOND: {
assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);		assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);

const InstructionMapping &SMapping = getInstructionMapping(		const InstructionMapping &SMapping = getInstructionMapping(
1, 1, getOperandsMapping(		1, 1, getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1), nullptr}),		{AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1), nullptr}),
2); // Num Operands		2); // Num Operands
AltMappings.push_back(&SMapping);		AltMappings.push_back(&SMapping);

const InstructionMapping &VMapping = getInstructionMapping(		const InstructionMapping &VMapping = getInstructionMapping(
1, 1, getOperandsMapping(		1, 1, getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), nullptr }),		{AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), nullptr }),
2); // Num Operands		2); // Num Operands
AltMappings.push_back(&VMapping);		AltMappings.push_back(&VMapping);
return AltMappings;		return AltMappings;
}		}
default:		default:
break;		break;
}		}
return RegisterBankInfo::getInstrAlternativeMappings(MI);		return RegisterBankInfo::getInstrAlternativeMappings(MI);
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {

if (MI.getOperand(OpdIdx).isIntrinsicID())		if (MI.getOperand(OpdIdx).isIntrinsicID())
OpdsMapping[OpdIdx++] = nullptr;		OpdsMapping[OpdIdx++] = nullptr;

unsigned Reg1 = MI.getOperand(OpdIdx).getReg();		unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);		unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);

unsigned DefaultBankID = Size1 == 1 ?		unsigned DefaultBankID = Size1 == 1 ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;		AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID);		unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID);

OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);		OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);

for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {		for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);		unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
unsigned BankID = Size == 1 ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;		unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);		OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);
}		}

return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),		return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
MI.getNumOperands());		MI.getNumOperands());
}		}

const RegisterBankInfo::InstructionMapping &		const RegisterBankInfo::InstructionMapping &
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines	case AMDGPU::G_ANYEXT: {

OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);		OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);		OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);
break;		break;
}		}
case AMDGPU::G_FCMP: {		case AMDGPU::G_FCMP: {
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();		unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);		unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1);		OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
OpdsMapping[1] = nullptr; // Predicate Operand.		OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);		OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);		OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
break;		break;
}		}
case AMDGPU::G_GEP: {		case AMDGPU::G_GEP: {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
if (!MI.getOperand(i).isReg())		if (!MI.getOperand(i).isReg())
Show All 23 Lines	AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}		}

case AMDGPU::G_ICMP: {		case AMDGPU::G_ICMP: {
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();		unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);		unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);		unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&		unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID ?		Op3Bank == AMDGPU::SGPRRegBankID ?
AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;		AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);		OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
OpdsMapping[1] = nullptr; // Predicate Operand.		OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);		OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);		OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
break;		break;
}		}


▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines	case AMDGPU::G_SELECT: {
unsigned Op1Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,		unsigned Op1Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
AMDGPU::SGPRRegBankID);		AMDGPU::SGPRRegBankID);
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);		unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);		unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
bool SGPRSrcs = Op1Bank == AMDGPU::SCCRegBankID &&		bool SGPRSrcs = Op1Bank == AMDGPU::SCCRegBankID &&
Op2Bank == AMDGPU::SGPRRegBankID &&		Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID;		Op3Bank == AMDGPU::SGPRRegBankID;
unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;		unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;		Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);		OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);		OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);		OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);		OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
break;		break;
}		}

case AMDGPU::G_LOAD:		case AMDGPU::G_LOAD:
Show All 12 Lines	AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_ATOMIC_CMPXCHG: {		case AMDGPU::G_ATOMIC_CMPXCHG: {
return getDefaultMappingAllVGPR(MI);		return getDefaultMappingAllVGPR(MI);
}		}
case AMDGPU::G_BRCOND: {		case AMDGPU::G_BRCOND: {
unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,		unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
AMDGPU::SGPRRegBankID);		AMDGPU::SGPRRegBankID);
assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);		assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
if (Bank != AMDGPU::SCCRegBankID)		if (Bank != AMDGPU::SCCRegBankID)
Bank = AMDGPU::SGPRRegBankID;		Bank = AMDGPU::VCCRegBankID;

OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1);		OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1);
break;		break;
}		}
}		}

return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),		return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
MI.getNumOperands());		MI.getNumOperands());
}		}

lib/Target/AMDGPU/AMDGPURegisterBanks.td

	Show All 9 Lines
	def SGPRRegBank : RegisterBank<"SGPR",			def SGPRRegBank : RegisterBank<"SGPR",
	[SReg_32, SReg_64, SReg_128, SReg_256, SReg_512]			[SReg_32, SReg_64, SReg_128, SReg_256, SReg_512]
	>;			>;

	def VGPRRegBank : RegisterBank<"VGPR",			def VGPRRegBank : RegisterBank<"VGPR",
	[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512]			[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512]
	>;			>;

	def SCCRegBank : RegisterBank <"SCC", [SCC_CLASS ]>;			def SCCRegBank : RegisterBank <"SCC", [SCC_CLASS]>;

				// It is helpful to distinguish conditions from ordinary SGPRs.
				def VCCRegBank : RegisterBank <"VCC", [SReg_64]>;

test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir

	Show All 25 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: wqm_vote_vcc			; CHECK-LABEL: name: wqm_vote_vcc
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
	; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[ICMP]](s1)			; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
				; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	%3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2			%3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
	...			...

	---			---
	name: wqm_vote_sgpr			name: wqm_vote_sgpr
	Show All 13 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir

	Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: and_i1_vcc_vcc			; CHECK-LABEL: name: and_i1_vcc_vcc
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
	; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
	; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[ICMP]], [[ICMP1]]			; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
				; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
				; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
	; CHECK: S_NOP 0, implicit [[AND]](s1)			; CHECK: S_NOP 0, implicit [[AND]](s1)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32) = G_CONSTANT i64 0			%2:_(s32) = G_CONSTANT i64 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_AND %4, %5			%6:_(s1) = G_AND %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
	...			...

	---			---
	name: and_i1_scc_vcc			name: and_i1_scc_vcc
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: and_i1_scc_vcc			; CHECK-LABEL: name: and_i1_scc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
	; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
	; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
	; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)			; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
	; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[ICMP1]]			; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
				; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
	; CHECK: S_NOP 0, implicit [[AND]](s1)			; CHECK: S_NOP 0, implicit [[AND]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32) = G_CONSTANT i64 0			%2:_(s32) = G_CONSTANT i64 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_AND %4, %5			%6:_(s1) = G_AND %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	body: \|			body: \|
	bb.0.entry:			bb.0.entry:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: and_i1_s_trunc_vcc			; CHECK-LABEL: name: and_i1_s_trunc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)			; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
	; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[ICMP]]			; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
				; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]]
	; CHECK: S_NOP 0, implicit [[AND]](s1)			; CHECK: S_NOP 0, implicit [[AND]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_TRUNC %0			%2:_(s1) = G_TRUNC %0
	%3:_(s1) = G_ICMP intpred(ne), %0, %1			%3:_(s1) = G_ICMP intpred(ne), %0, %1
	%4:_(s1) = G_AND %2, %3			%4:_(s1) = G_AND %2, %3
	S_NOP 0, implicit %4			S_NOP 0, implicit %4
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast \| FileCheck %s		# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast \| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy \| FileCheck %s		# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy \| FileCheck %s

---		---
name: brcond_vcc_cond		name: brcond_vcc_cond
legalized: true		legalized: true
body: \|		body: \|
; CHECK-LABEL: name: brcond_vcc_cond		; CHECK-LABEL: name: brcond_vcc_cond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1		; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
; CHECK: bb.1:		; CHECK: bb.1:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1		%2:_(s1) = G_ICMP intpred(ne), %0, %1
Show All 29 Lines
name: brcond_sgpr_cond		name: brcond_sgpr_cond
legalized: true		legalized: true
body: \|		body: \|
; CHECK-LABEL: name: brcond_sgpr_cond		; CHECK-LABEL: name: brcond_sgpr_cond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1		; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
; CHECK: bb.1:		; CHECK: bb.1:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $sgpr0		liveins: $sgpr0
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s1) = G_TRUNC %0		%1:_(s1) = G_TRUNC %0
G_BRCOND %1, %bb.1		G_BRCOND %1, %bb.1

bb.1:		bb.1:
...		...

---		---
name: brcond_vgpr_cond		name: brcond_vgpr_cond
legalized: true		legalized: true
body: \|		body: \|
; CHECK-LABEL: name: brcond_vgpr_cond		; CHECK-LABEL: name: brcond_vgpr_cond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1		; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
; CHECK: bb.1:		; CHECK: bb.1:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $vgpr0		liveins: $vgpr0
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0		%1:_(s1) = G_TRUNC %0
G_BRCOND %1, %bb.1		G_BRCOND %1, %bb.1
Show All 11 Lines
body: \|		body: \|
; CHECK-LABEL: name: empty_block_vgpr_brcond		; CHECK-LABEL: name: empty_block_vgpr_brcond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: bb.1:		; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1		; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
; CHECK: bb.2:		; CHECK: bb.2:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $vgpr0		liveins: $vgpr0
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0		%1:_(s1) = G_TRUNC %0

Show All 11 Lines
body: \|		body: \|
; CHECK-LABEL: name: copy_first_inst_brcond		; CHECK-LABEL: name: copy_first_inst_brcond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: bb.1:		; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1		; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
; CHECK: bb.2:		; CHECK: bb.2:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $vgpr0		liveins: $vgpr0
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0

bb.1:		bb.1:
Show All 11 Lines	body: \|
; CHECK-LABEL: name: copy_middle_inst_brcond		; CHECK-LABEL: name: copy_middle_inst_brcond
; CHECK: bb.0.entry:		; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)		; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: bb.1:		; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: S_NOP 0		; CHECK: S_NOP 0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1		; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
; CHECK: bb.2:		; CHECK: bb.2:
bb.0.entry:		bb.0.entry:
successors: %bb.1		successors: %bb.1
liveins: $vgpr0		liveins: $vgpr0
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0

bb.1:		bb.1:
%1:_(s1) = G_TRUNC %0		%1:_(s1) = G_TRUNC %0
S_NOP 0		S_NOP 0
G_BRCOND %1, %bb.1		G_BRCOND %1, %bb.1

bb.2:		bb.2:
...		...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy \| FileCheck %s

	---			---
	name: fcmp_ss			name: fcmp_ss
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1
	; CHECK-LABEL: name: fcmp_ss			; CHECK-LABEL: name: fcmp_ss
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
	; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY2]]			; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY2]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $sgpr1			%1:_(s32) = COPY $sgpr1
	%2:_(s1) = G_FCMP floatpred(uge), %0(s32), %1			%2:_(s1) = G_FCMP floatpred(uge), %0(s32), %1
	...			...

	---			---
	name: fcmp_sv			name: fcmp_sv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: fcmp_sv			; CHECK-LABEL: name: fcmp_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]]			; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_FCMP floatpred(uge), %0, %1			%2:_(s1) = G_FCMP floatpred(uge), %0, %1
	...			...

	---			---
	name: fcmp_vs			name: fcmp_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: fcmp_vs			; CHECK-LABEL: name: fcmp_vs
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY1]](s32), [[COPY2]]			; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY1]](s32), [[COPY2]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_FCMP floatpred(uge), %1, %0			%2:_(s1) = G_FCMP floatpred(uge), %1, %0
	...			...

	---			---
	name: fcmp_vv			name: fcmp_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: fcmp_vv			; CHECK-LABEL: name: fcmp_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP floatpred(uge), [[COPY]](s32), [[COPY1]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP floatpred(uge), [[COPY]](s32), [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s1) = G_ICMP floatpred(uge), %0, %1			%2:_(s1) = G_ICMP floatpred(uge), %0, %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir

	Show All 22 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: icmp_sv			; CHECK-LABEL: name: icmp_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	...			...

	---			---
	name: icmp_vs			name: icmp_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: icmp_vs			; CHECK-LABEL: name: icmp_vs
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_ICMP intpred(ne), %1, %0			%2:_(s1) = G_ICMP intpred(ne), %1, %0
	...			...

	---			---
	name: icmp_vv			name: icmp_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: icmp_vv			; CHECK-LABEL: name: icmp_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir

Show All 39 Lines	bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: sadde_s32_vss		; FAST-LABEL: name: sadde_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]		; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: sadde_s32_vss		; GREEDY-LABEL: name: sadde_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]		; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0		%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3		%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4		%5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
...		...
---		---
name: sadde_s32_ssv		name: sadde_s32_ssv
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: sadde_s32_ssv		; FAST-LABEL: name: sadde_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]		; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: sadde_s32_ssv		; GREEDY-LABEL: name: sadde_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]		; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0		%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...		...

---		---
name: sadde_s32_vvs		name: sadde_s32_vvs
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: sadde_s32_vvs		; FAST-LABEL: name: sadde_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: sadde_s32_vvs		; GREEDY-LABEL: name: sadde_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...		...

---		---
Show All 12 Lines	bb.0:
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]		; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: sadde_s32_sss_noscc		; GREEDY-LABEL: name: sadde_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[TRUNC]]		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2		%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...		...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-saddo.mir

	Show All 22 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: saddo_s32_sv			; CHECK-LABEL: name: saddo_s32_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY2]], [[COPY1]]			; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:vcc(s1) = G_SADDO [[COPY2]], [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32), %3:_(s1) = G_SADDO %0, %1			%2:_(s32), %3:_(s1) = G_SADDO %0, %1
	...			...

	---			---
	name: saddo_s32_vs			name: saddo_s32_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: saddo_s32_vs			; CHECK-LABEL: name: saddo_s32_vs
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
	; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY]], [[COPY2]]			; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:vcc(s1) = G_SADDO [[COPY]], [[COPY2]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $sgpr0			%1:_(s32) = COPY $sgpr0
	%2:_(s32), %3:_(s1) = G_SADDO %0, %1			%2:_(s32), %3:_(s1) = G_SADDO %0, %1
	...			...

	---			---
	name: saddo_s32_vv			name: saddo_s32_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: saddo_s32_vv			; CHECK-LABEL: name: saddo_s32_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY]], [[COPY1]]			; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:vcc(s1) = G_SADDO [[COPY]], [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32), %3:_(s1) = G_SADDO %0, %1			%2:_(s32), %3:_(s1) = G_SADDO %0, %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir

	Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true

	# GCN-LABEL: name: select_ssv			# GCN-LABEL: name: select_ssv
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2			# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]			# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
	# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]			# GCN: [[SCC_S:%[0-9]+]]:vcc(s1) = COPY [[SCC]]
	# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]			# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
	# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2_V]], [[VGPR0]]			# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2_V]], [[VGPR0]]
	# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2]], [[VGPR0]]			# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2]], [[VGPR0]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0			liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $sgpr1			%1:_(s32) = COPY $sgpr1
	%2:_(s32) = COPY $sgpr2			%2:_(s32) = COPY $sgpr2
	%3:_(s32) = COPY $vgpr0			%3:_(s32) = COPY $vgpr0
	%4:_(s1) = G_ICMP intpred(ne), %0, %1			%4:_(s1) = G_ICMP intpred(ne), %0, %1
	%5:_(s32) = G_SELECT %4, %2, %3			%5:_(s32) = G_SELECT %4, %2, %3

	...			...

	---			---
	name: select_svs			name: select_svs
	legalized: true			legalized: true

	# GCN-LABEL: name: select_svs			# GCN-LABEL: name: select_svs
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2			# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]			# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
	# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]			# GCN: [[SCC_S:%[0-9]+]]:vcc(s1) = COPY [[SCC]]
	# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]			# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
	# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2_V]]			# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2_V]]
	# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2]]			# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0			liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	Show All 9 Lines
	legalized: true			legalized: true

	# GCN-LABEL: name: select_svv			# GCN-LABEL: name: select_svv
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]			# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
	# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]			# GCN: [[SCC_S:%[0-9]+]]:vcc(s1) = COPY [[SCC]]
	# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[VGPR1]]			# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[VGPR1]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1			liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $sgpr1			%1:_(s32) = COPY $sgpr1
	%2:_(s32) = COPY $vgpr0			%2:_(s32) = COPY $vgpr0
	%3:_(s32) = COPY $vgpr1			%3:_(s32) = COPY $vgpr1
	%4:_(s1) = G_ICMP intpred(ne), %0, %1			%4:_(s1) = G_ICMP intpred(ne), %0, %1
	%5:_(s32) = G_SELECT %4, %2, %3			%5:_(s32) = G_SELECT %4, %2, %3
	...			...

	---			---
	name: select_vss			name: select_vss
	legalized: true			legalized: true

	# GCN-LABEL: name: select_vss			# GCN-LABEL: name: select_vss
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]			# GCN: [[VCC:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
	# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]			# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
	# GCN: [[SGPR1_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR1]]			# GCN: [[SGPR1_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR1]]
	# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[SGPR1_V]]			# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[SGPR1_V]]
	# GREDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[SGPR1_V]]			# GREDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[SGPR1_V]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1			liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
	Show All 9 Lines
	name: select_vsv			name: select_vsv
	legalized: true			legalized: true

	# GCN-LABEL: name: select_vsv			# GCN-LABEL: name: select_vsv
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
	# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]			# GCN: [[VCC:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
	# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]			# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
	# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[VGPR2]]			# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[VGPR2]]
	# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[VGPR2]]			# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[VGPR2]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32) = COPY $vgpr1			%2:_(s32) = COPY $vgpr1
	%3:_(s32) = COPY $vgpr2			%3:_(s32) = COPY $vgpr2
	%4:_(s1) = G_ICMP intpred(ne), %1, %2			%4:_(s1) = G_ICMP intpred(ne), %1, %2
	%5:_(s32) = G_SELECT %4, %0, %3			%5:_(s32) = G_SELECT %4, %0, %3
	...			...

	---			---
	name: select_vvs			name: select_vvs
	legalized: true			legalized: true

	# GCN-LABEL: name: select_vvs			# GCN-LABEL: name: select_vvs
	# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
	# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]			# GCN: [[VCC:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
	# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]			# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
	# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0_V]]			# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0_V]]
	# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0]]			# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32) = COPY $vgpr1			%2:_(s32) = COPY $vgpr1
	%3:_(s32) = COPY $vgpr2			%3:_(s32) = COPY $vgpr2
	%4:_(s1) = G_ICMP intpred(ne), %1, %2			%4:_(s1) = G_ICMP intpred(ne), %1, %2
	%5:_(s32) = G_SELECT %4, %3, %0			%5:_(s32) = G_SELECT %4, %3, %0
	...			...

	---			---
	name: select_vvv			name: select_vvv
	legalized: true			legalized: true

	# GCN-LABEL: name: select_vvv			# GCN-LABEL: name: select_vvv
	# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
	# GCN: [[VGPR3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3			# GCN: [[VGPR3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
	# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]			# GCN: [[VCC:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
	# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[VGPR3]]			# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[VGPR3]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3			liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32) = COPY $vgpr2			%2:_(s32) = COPY $vgpr2
	%3:_(s32) = COPY $vgpr3			%3:_(s32) = COPY $vgpr3
	%4:_(s1) = G_ICMP intpred(ne), %0, %1			%4:_(s1) = G_ICMP intpred(ne), %0, %1
	%5:_(s32) = G_SELECT %4, %2, %3			%5:_(s32) = G_SELECT %4, %2, %3
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir

Show All 39 Lines	bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: ssube_s32_vss		; FAST-LABEL: name: ssube_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]		; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: ssube_s32_vss		; GREEDY-LABEL: name: ssube_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]		; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0		%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3		%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4		%5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
...		...
---		---
name: ssube_s32_ssv		name: ssube_s32_ssv
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: ssube_s32_ssv		; FAST-LABEL: name: ssube_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]		; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: ssube_s32_ssv		; GREEDY-LABEL: name: ssube_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]		; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0		%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...		...

---		---
name: ssube_s32_vvs		name: ssube_s32_vvs
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: ssube_s32_vvs		; FAST-LABEL: name: ssube_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: ssube_s32_vvs		; GREEDY-LABEL: name: ssube_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...		...

---		---
Show All 12 Lines	bb.0:
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]		; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: ssubee_s32_sss_noscc		; GREEDY-LABEL: name: ssubee_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[TRUNC]]		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2		%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...		...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssubo.mir

	Show All 23 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: ssubo_s32_sv			; CHECK-LABEL: name: ssubo_s32_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY2]], [[COPY1]]			; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:vcc(s1) = G_SSUBO [[COPY2]], [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32), %3:_(s1) = G_SSUBO %0, %1			%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
	...			...

	---			---
	name: ssubo_s32_vs			name: ssubo_s32_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: ssubo_s32_vs			; CHECK-LABEL: name: ssubo_s32_vs
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
	; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY]], [[COPY2]]			; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:vcc(s1) = G_SSUBO [[COPY]], [[COPY2]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $sgpr0			%1:_(s32) = COPY $sgpr0
	%2:_(s32), %3:_(s1) = G_SSUBO %0, %1			%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
	...			...

	---			---
	name: ssubo_s32_vv			name: ssubo_s32_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: ssubo_s32_vv			; CHECK-LABEL: name: ssubo_s32_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY]], [[COPY1]]			; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:vcc(s1) = G_SSUBO [[COPY]], [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32), %3:_(s1) = G_SSUBO %0, %1			%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir

Show All 38 Lines	bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: uadde_s32_vss		; FAST-LABEL: name: uadde_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]		; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: uadde_s32_vss		; GREEDY-LABEL: name: uadde_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]		; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0		%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3		%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4		%5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
...		...
---		---
name: uadde_s32_ssv		name: uadde_s32_ssv
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: uadde_s32_ssv		; FAST-LABEL: name: uadde_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]		; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: uadde_s32_ssv		; GREEDY-LABEL: name: uadde_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]		; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0		%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...		...

---		---
name: uadde_s32_vvs		name: uadde_s32_vvs
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: uadde_s32_vvs		; FAST-LABEL: name: uadde_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: uadde_s32_vvs		; GREEDY-LABEL: name: uadde_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...		...

---		---
Show All 12 Lines	bb.0:
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]		; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: uadde_s32_sss_noscc		; GREEDY-LABEL: name: uadde_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[TRUNC]]		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2		%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3		%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...		...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir

	Show All 23 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: uaddo_s32_sv			; CHECK-LABEL: name: uaddo_s32_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY2]], [[COPY1]]			; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY2]], [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32), %3:_(s1) = G_UADDO %0, %1			%2:_(s32), %3:_(s1) = G_UADDO %0, %1
	...			...

	---			---
	name: uaddo_s32_vs			name: uaddo_s32_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: uaddo_s32_vs			; CHECK-LABEL: name: uaddo_s32_vs
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
	; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY]], [[COPY2]]			; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY2]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $sgpr0			%1:_(s32) = COPY $sgpr0
	%2:_(s32), %3:_(s1) = G_UADDO %0, %1			%2:_(s32), %3:_(s1) = G_UADDO %0, %1
	...			...

	---			---
	name: uaddo_s32_vv			name: uaddo_s32_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: uaddo_s32_vv			; CHECK-LABEL: name: uaddo_s32_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY]], [[COPY1]]			; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32), %3:_(s1) = G_UADDO %0, %1			%2:_(s32), %3:_(s1) = G_UADDO %0, %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir

Show All 39 Lines	bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: usube_s32_vss		; FAST-LABEL: name: usube_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]		; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: usube_s32_vss		; GREEDY-LABEL: name: usube_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]		; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0		%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3		%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4		%5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
...		...
---		---
name: usube_s32_ssv		name: usube_s32_ssv
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: usube_s32_ssv		; FAST-LABEL: name: usube_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]		; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: usube_s32_ssv		; GREEDY-LABEL: name: usube_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]		; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0		%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...		...

---		---
name: usube_s32_vvs		name: usube_s32_vvs
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: usube_s32_vvs		; FAST-LABEL: name: usube_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: usube_s32_vvs		; GREEDY-LABEL: name: usube_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...		...

---		---
Show All 12 Lines	bb.0:
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]		; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: usube_s32_sss_noscc		; GREEDY-LABEL: name: usube_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[TRUNC]]		; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2		%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2		%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3		%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...		...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir

	Show All 23 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: usubo_s32_sv			; CHECK-LABEL: name: usubo_s32_sv
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY2]], [[COPY1]]			; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:vcc(s1) = G_USUBO [[COPY2]], [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32), %3:_(s1) = G_USUBO %0, %1			%2:_(s32), %3:_(s1) = G_USUBO %0, %1
	...			...

	---			---
	name: usubo_s32_vs			name: usubo_s32_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: usubo_s32_vs			; CHECK-LABEL: name: usubo_s32_vs
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
	; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY]], [[COPY2]]			; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:vcc(s1) = G_USUBO [[COPY]], [[COPY2]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $sgpr0			%1:_(s32) = COPY $sgpr0
	%2:_(s32), %3:_(s1) = G_USUBO %0, %1			%2:_(s32), %3:_(s1) = G_USUBO %0, %1
	...			...

	---			---
	name: usubo_s32_vv			name: usubo_s32_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: usubo_s32_vv			; CHECK-LABEL: name: usubo_s32_vv
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY]], [[COPY1]]			; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:vcc(s1) = G_USUBO [[COPY]], [[COPY1]]
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32), %3:_(s1) = G_USUBO %0, %1			%2:_(s32), %3:_(s1) = G_USUBO %0, %1
	...			...

This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU/GlobalISel: Introduce vcc reg bankClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 178841

lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

lib/Target/AMDGPU/AMDGPURegisterBanks.td

test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-saddo.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssubo.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir

AMDGPU/GlobalISel: Introduce vcc reg bank
ClosedPublic