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Differential D55751

AMDGPU/GlobalISel: RegBankSelect for add/sub with carry in
ClosedPublic

Authored by arsenm on Dec 16 2018, 3:50 PM.

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Reviewers
tstellar

Diff Detail

Event Timeline

arsenm created this revision.Dec 16 2018, 3:50 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 16 2018, 3:50 PM
arsenm added a parent revision: D55693: AMDGPU/GlobalISel: Fix ValueMapping tables for i1.Dec 16 2018, 3:50 PM
tstellar added a comment.Dec 19 2018, 1:56 PM

This is a duplicate of D55695?

arsenm updated this revision to Diff 178997.Dec 19 2018, 5:42 PM
arsenm retitled this revision from AMDGPU/GlobalISel: RegBankSelect for add/sub with carry out to AMDGPU/GlobalISel: RegBankSelect for add/sub with carry in.

Attach correct patch

arsenm added a parent revision: D55695: AMDGPU/GlobalISel: RegBankSelect for add/sub with carry out.Dec 19 2018, 5:43 PM
arsenm added a comment.Jan 3 2019, 5:51 PM

ping

tstellar accepted this revision.Jan 7 2019, 9:14 AM

LGTM.

This revision is now accepted and ready to land.Jan 7 2019, 9:14 AM
arsenm closed this revision.Jan 7 2019, 5:13 PM

r350592

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
23 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
68 lines
68 lines
68 lines
68 lines

Diff 178414

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
setAction({G_ADD, S32}, Legal); setAction({G_ADD, S32}, Legal);
setAction({G_SUB, S32}, Legal); setAction({G_SUB, S32}, Legal);
setAction({G_MUL, S32}, Legal); setAction({G_MUL, S32}, Legal);
setAction({G_AND, S32}, Legal); setAction({G_AND, S32}, Legal);
setAction({G_OR, S32}, Legal); setAction({G_OR, S32}, Legal);
setAction({G_XOR, S32}, Legal); setAction({G_XOR, S32}, Legal);
getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO})
.legalFor({{S32, S1}});
setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, V2S16}, Legal);
setAction({G_BITCAST, 1, S32}, Legal); setAction({G_BITCAST, 1, S32}, Legal);
setAction({G_BITCAST, S32}, Legal); setAction({G_BITCAST, S32}, Legal);
setAction({G_BITCAST, 1, V2S16}, Legal); setAction({G_BITCAST, 1, V2S16}, Legal);
getActionDefinitionsBuilder(G_FCONSTANT) getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({S32, S64}); .legalFor({S32, S64});
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const { bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
if (!MI.getOperand(i).isReg()) if (!MI.getOperand(i).isReg())
continue; continue;
unsigned Reg = MI.getOperand(i).getReg(); unsigned Reg = MI.getOperand(i).getReg();
const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID) if (Bank->getID() == AMDGPU::VGPRRegBankID)
return false; return false;
assert(Bank->getID() == AMDGPU::SGPRRegBankID ||
Bank->getID() == AMDGPU::SCCRegBankID);
}
} }
return true; return true;
} }
const RegisterBankInfo::InstructionMapping & const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const { AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands()); SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); unsigned BankID = Size == 1 ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
} }
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping), return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
MI.getNumOperands()); MI.getNumOperands());
} }
const RegisterBankInfo::InstructionMapping & const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const { AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands()); SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
unsigned OpdIdx = 0; unsigned OpdIdx = 0;
unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0); OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
if (MI.getOperand(OpdIdx).isIntrinsicID()) if (MI.getOperand(OpdIdx).isIntrinsicID())
OpdsMapping[OpdIdx++] = nullptr; OpdsMapping[OpdIdx++] = nullptr;
unsigned Reg1 = MI.getOperand(OpdIdx).getReg(); unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI); unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
unsigned DefaultBankID = Size1 == 1 ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID);
OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1); OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) { for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
} }
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping), return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_SUB: case AMDGPU::G_SUB:
case AMDGPU::G_MUL: case AMDGPU::G_MUL:
case AMDGPU::G_AND: case AMDGPU::G_AND:
case AMDGPU::G_OR: case AMDGPU::G_OR:
case AMDGPU::G_XOR: case AMDGPU::G_XOR:
case AMDGPU::G_SHL: case AMDGPU::G_SHL:
case AMDGPU::G_LSHR: case AMDGPU::G_LSHR:
case AMDGPU::G_ASHR: case AMDGPU::G_ASHR:
case AMDGPU::G_UADDO:
case AMDGPU::G_SADDO:
case AMDGPU::G_USUBO:
case AMDGPU::G_SSUBO:
if (isSALUMapping(MI)) if (isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AMDGPU::G_FADD: case AMDGPU::G_FADD:
case AMDGPU::G_FSUB: case AMDGPU::G_FSUB:
case AMDGPU::G_FPTOSI: case AMDGPU::G_FPTOSI:
case AMDGPU::G_FPTOUI: case AMDGPU::G_FPTOUI:
▲ Show 20 Lines • Show All 283 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-saddo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: saddo_s32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: saddo_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[SADDO:%[0-9]+]]:sgpr(s32), [[SADDO1:%[0-9]+]]:scc(s1) = G_SADDO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32), %3:_(s1) = G_SADDO %0, %1
...
---
name: saddo_s32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: saddo_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY2]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32), %3:_(s1) = G_SADDO %0, %1
...
---
name: saddo_s32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: saddo_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32), %3:_(s1) = G_SADDO %0, %1
...
---
name: saddo_s32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: saddo_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[SADDO:%[0-9]+]]:vgpr(s32), [[SADDO1:%[0-9]+]]:sgpr(s1) = G_SADDO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32), %3:_(s1) = G_SADDO %0, %1
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssubo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: ssubo_s32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: ssubo_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[SSUBO:%[0-9]+]]:sgpr(s32), [[SSUBO1:%[0-9]+]]:scc(s1) = G_SSUBO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
...
---
name: ssubo_s32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: ssubo_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY2]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
...
---
name: ssubo_s32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: ssubo_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
...
---
name: ssubo_s32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: ssubo_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[SSUBO:%[0-9]+]]:vgpr(s32), [[SSUBO1:%[0-9]+]]:sgpr(s1) = G_SSUBO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: uaddo_s32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: uaddo_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:scc(s1) = G_UADDO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
...
---
name: uaddo_s32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: uaddo_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY2]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
...
---
name: uaddo_s32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: uaddo_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
...
---
name: uaddo_s32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: uaddo_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: usubo_s32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: usubo_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[USUBO:%[0-9]+]]:sgpr(s32), [[USUBO1:%[0-9]+]]:scc(s1) = G_USUBO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
...
---
name: usubo_s32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: usubo_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY2]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
...
---
name: usubo_s32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: usubo_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
...
---
name: usubo_s32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: usubo_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[USUBO:%[0-9]+]]:vgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s1) = G_USUBO [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
...