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AMDGPU: Legalize/regbankselect frame_index
ClosedPublic

Authored by arsenm on Dec 12 2018, 6:43 PM.

Reviewers

tstellar
rampitec

LGTM

This revision is now accepted and ready to land.Dec 12 2018, 6:51 PM

r349468

Path

Size

lib/

Target/

AMDGPU/

2 lines

1 line

test/

CodeGen/

AMDGPU/

GlobalISel/

24 lines

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines	AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
getActionDefinitionsBuilder(G_CONSTANT)		getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S1, S32, S64});		.legalFor({S1, S32, S64});

// FIXME: i1 operands to intrinsics should always be legal, but other i1		// FIXME: i1 operands to intrinsics should always be legal, but other i1
// values may not be legal. We need to figure out how to distinguish		// values may not be legal. We need to figure out how to distinguish
// between these two scenarios.		// between these two scenarios.
setAction({G_CONSTANT, S1}, Legal);		setAction({G_CONSTANT, S1}, Legal);

		setAction({G_FRAME_INDEX, PrivatePtr}, Legal);

getActionDefinitionsBuilder(		getActionDefinitionsBuilder(
{ G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})		{ G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
.legalFor({S32, S64});		.legalFor({S32, S64});

// Use actual fsub instruction		// Use actual fsub instruction
setAction({G_FSUB, S32}, Legal);		setAction({G_FSUB, S32}, Legal);

// Must use fadd + fneg		// Must use fadd + fneg
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

Show First 20 Lines • Show All 360 Lines • ▼ Show 20 Lines	case AMDGPU::G_FMA:
return getDefaultMappingVOP(MI);		return getDefaultMappingVOP(MI);
case AMDGPU::G_IMPLICIT_DEF: {		case AMDGPU::G_IMPLICIT_DEF: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();		unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);		OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break;		break;
}		}
case AMDGPU::G_FCONSTANT:		case AMDGPU::G_FCONSTANT:
case AMDGPU::G_CONSTANT:		case AMDGPU::G_CONSTANT:
		case AMDGPU::G_FRAME_INDEX:
case AMDGPU::G_BLOCK_ADDR: {		case AMDGPU::G_BLOCK_ADDR: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();		unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);		OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break;		break;
}		}
case AMDGPU::G_INSERT: {		case AMDGPU::G_INSERT: {
unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :		unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
AMDGPU::VGPRRegBankID;		AMDGPU::VGPRRegBankID;
▲ Show 20 Lines • Show All 257 Lines • Show Last 20 Lines

				# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
				# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast \| FileCheck %s
				# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy \| FileCheck %s

				--- \|
				target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
				define void @test_frame_index_p5() {
				%ptr0 = alloca i32, addrspace(5)
				ret void
				}
				...
				---
				name: test_frame_index_p5
				legalized: true
				stack:
				- { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
				body: \|
				bb.0:
				; CHECK-LABEL: name: test_frame_index_p5
				; CHECK: [[FRAME_INDEX:%[0-9]+]]:sgpr(p5) = G_FRAME_INDEX %stack.0.ptr0
				%0:_(p5) = G_FRAME_INDEX %stack.0.ptr0

				...