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Differential D55635

AMDGPU: Legalize/regbankselect fma
ClosedPublic

Authored by arsenm on Dec 12 2018, 6:41 PM.

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Reviewers
tstellar
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Dec 12 2018, 6:41 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptDec 12 2018, 6:41 PM
rampitec accepted this revision.Dec 12 2018, 6:50 PM

LGTM

This revision is now accepted and ready to land.Dec 12 2018, 6:50 PM
arsenm closed this revision.Dec 18 2018, 1:43 AM

r349467

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
1 line
test/
CodeGen/
AMDGPU/
GlobalISel/
35 lines
148 lines

Diff 177989

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S1, S32, S64}); .legalFor({S1, S32, S64});
// FIXME: i1 operands to intrinsics should always be legal, but other i1 // FIXME: i1 operands to intrinsics should always be legal, but other i1
// values may not be legal. We need to figure out how to distinguish // values may not be legal. We need to figure out how to distinguish
// between these two scenarios. // between these two scenarios.
setAction({G_CONSTANT, S1}, Legal); setAction({G_CONSTANT, S1}, Legal);
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{ G_FADD, G_FMUL, G_FNEG, G_FABS}) { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
.legalFor({S32, S64}); .legalFor({S32, S64});
// Use actual fsub instruction // Use actual fsub instruction
setAction({G_FSUB, S32}, Legal); setAction({G_FSUB, S32}, Legal);
// Must use fadd + fneg // Must use fadd + fneg
setAction({G_FSUB, S64}, Lower); setAction({G_FSUB, S64}, Lower);
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Lines case AMDGPU::G_SHL:
if (isSALUMapping(MI)) if (isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AMDGPU::G_FADD: case AMDGPU::G_FADD:
case AMDGPU::G_FPTOSI: case AMDGPU::G_FPTOSI:
case AMDGPU::G_FPTOUI: case AMDGPU::G_FPTOUI:
case AMDGPU::G_FMUL: case AMDGPU::G_FMUL:
case AMDGPU::G_FMA:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
case AMDGPU::G_IMPLICIT_DEF: { case AMDGPU::G_IMPLICIT_DEF: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break; break;
} }
case AMDGPU::G_FCONSTANT: case AMDGPU::G_FCONSTANT:
case AMDGPU::G_CONSTANT: { case AMDGPU::G_CONSTANT: {
▲ Show 20 Lines • Show All 264 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_fma_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_fma
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = G_FMA %0, %1, %2
$vgpr0 = COPY %3
...
---
name: test_fma_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_fma
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[COPY]], [[COPY1]]
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = COPY $vgpr4_vgpr5
%3:_(s64) = G_FMA %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fma_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-LABEL: name: fma_sss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_vss
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1
; CHECK-LABEL: name: fma_vss
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_svs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $sgpr1
; CHECK-LABEL: name: fma_svs
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
; CHECK-LABEL: name: fma_ssv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY3]], [[COPY2]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_vvs
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0
; CHECK-LABEL: name: fma_vvs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_vsv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $vgpr1
; CHECK-LABEL: name: fma_vsv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY3]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr1
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_svv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1
; CHECK-LABEL: name: fma_svv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s32) = G_FMA %0, %1, %2
...
---
name: fma_vvv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: fma_vvv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; CHECK: [[FMA:%[0-9]+]]:vgpr(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = G_FMA %0, %1, %2
...