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Differential D55634

AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub
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Authored by arsenm on Dec 12 2018, 6:41 PM.

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Reviewers
tstellar
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Dec 12 2018, 6:41 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 12 2018, 6:41 PM
rampitec added inline comments.Dec 12 2018, 6:48 PM
test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
12

So, where is the abs operation itself?

test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
12

And where is neg?

arsenm updated this revision to Diff 178117.Dec 13 2018, 12:16 PM

Fix missing copy in test

rampitec accepted this revision.Dec 13 2018, 12:22 PM

LGTM

This revision is now accepted and ready to land.Dec 13 2018, 12:22 PM
arsenm closed this revision.Dec 18 2018, 1:22 AM

r349463

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
4 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
26 lines
26 lines
36 lines
35 lines
35 lines

Diff 178117

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S1, S32, S64}); .legalFor({S1, S32, S64});
// FIXME: i1 operands to intrinsics should always be legal, but other i1 // FIXME: i1 operands to intrinsics should always be legal, but other i1
// values may not be legal. We need to figure out how to distinguish // values may not be legal. We need to figure out how to distinguish
// between these two scenarios. // between these two scenarios.
setAction({G_CONSTANT, S1}, Legal); setAction({G_CONSTANT, S1}, Legal);
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{ G_FADD, G_FMUL }) { G_FADD, G_FMUL, G_FNEG, G_FABS})
.legalFor({S32, S64}); .legalFor({S32, S64});
// Use actual fsub instruction
setAction({G_FSUB, S32}, Legal);
// Must use fadd + fneg
setAction({G_FSUB, S64}, Lower);
setAction({G_FCMP, S1}, Legal); setAction({G_FCMP, S1}, Legal);
setAction({G_FCMP, 1, S32}, Legal); setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal); setAction({G_FCMP, 1, S64}, Legal);
setAction({G_ZEXT, S64}, Legal); setAction({G_ZEXT, S64}, Legal);
setAction({G_ZEXT, 1, S32}, Legal); setAction({G_ZEXT, 1, S32}, Legal);
setAction({G_SEXT, S64}, Legal); setAction({G_SEXT, S64}, Legal);
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 404 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_BITCAST: case AMDGPU::G_BITCAST:
case AMDGPU::G_INTTOPTR: case AMDGPU::G_INTTOPTR:
case AMDGPU::G_PTRTOINT: case AMDGPU::G_PTRTOINT:
case AMDGPU::G_CTLZ: case AMDGPU::G_CTLZ:
case AMDGPU::G_CTLZ_ZERO_UNDEF: case AMDGPU::G_CTLZ_ZERO_UNDEF:
case AMDGPU::G_CTTZ: case AMDGPU::G_CTTZ:
case AMDGPU::G_CTTZ_ZERO_UNDEF: case AMDGPU::G_CTTZ_ZERO_UNDEF:
case AMDGPU::G_CTPOP: case AMDGPU::G_CTPOP:
case AMDGPU::G_BSWAP: { case AMDGPU::G_BSWAP:
case AMDGPU::G_FABS:
case AMDGPU::G_FNEG: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
break; break;
} }
case AMDGPU::G_TRUNC: { case AMDGPU::G_TRUNC: {
unsigned Dst = MI.getOperand(0).getReg(); unsigned Dst = MI.getOperand(0).getReg();
unsigned Src = MI.getOperand(1).getReg(); unsigned Src = MI.getOperand(1).getReg();
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_fabs_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fabs_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
%0:_(s32) = COPY $vgpr0
rampitecUnsubmitted
Not Done
ReplyInline Actions

So, where is the abs operation itself?

rampitec: So, where is the abs operation itself?
%1:_(s32) = G_FABS %0
...
---
name: test_fabs_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fabs_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_FABS %0
...

test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_fneg_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fneg_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
%0:_(s32) = COPY $vgpr0
rampitecUnsubmitted
Not Done
ReplyInline Actions

And where is neg?

rampitec: And where is neg?
%1:_(s32) = G_FNEG %0
...
---
name: test_fneg_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fneg_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_FNEG %0
...

test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_fsub_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_fsub_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[FSUB]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FSUB %0, %1
$vgpr0 = COPY %2
...
---
name: test_fsub_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_fsub_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_FSUB %0, %1
$vgpr0_vgpr1 = COPY %2
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fabs_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fabs_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[FABS:%[0-9]+]]:sgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...
---
name: fabs_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fabs_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[FABS:%[0-9]+]]:vgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fneg_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fneg_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY]]
; CHECK: $vgpr0 = COPY [[FNEG]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FNEG %0
$vgpr0 = COPY %1
...
---
name: fneg_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[FNEG:%[0-9]+]]:vgpr(s32) = G_FNEG [[COPY]]
; CHECK: $vgpr0 = COPY [[FNEG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FNEG %0
$vgpr0 = COPY %1
...