AMDGPU/GlobalISel: Legalize f64 fadd/fmul

[rampitec]

LGTM

[arsenm]

r349014

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
   getActionDefinitionsBuilder(G_CONSTANT)
     .legalFor({S1, S32, S64});
 
   // FIXME: i1 operands to intrinsics should always be legal, but other i1
   // values may not be legal.  We need to figure out how to distinguish
   // between these two scenarios.
   setAction({G_CONSTANT, S1}, Legal);
 
-  setAction({G_FADD, S32}, Legal);
+  getActionDefinitionsBuilder(
+    { G_FADD, G_FMUL })
+    .legalFor({S32, S64});
 
   setAction({G_FCMP, S1}, Legal);
   setAction({G_FCMP, 1, S32}, Legal);
   setAction({G_FCMP, 1, S64}, Legal);
 
-  setAction({G_FMUL, S32}, Legal);
-
   setAction({G_ZEXT, S64}, Legal);
   setAction({G_ZEXT, 1, S32}, Legal);
 
   setAction({G_SEXT, S64}, Legal);
   setAction({G_SEXT, 1, S32}, Legal);
 
   setAction({G_ANYEXT, S64}, Legal);
   setAction({G_ANYEXT, 1, S32}, Legal);

test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name:            test_fadd
+name: test_fadd_f32
 body: |
   bb.0.entry:
     liveins: $vgpr0, $vgpr1
     ; CHECK-LABEL: name: test_fadd
     ; CHECK: %2:_(s32) = G_FADD %0, %1
 
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = G_FADD %0, %1
     $vgpr0 = COPY %2
 ...
+---
+name: test_fadd_f64
+body: |
+  bb.0.entry:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s64) = G_FADD %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...

test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name:            test_fmul
+name: test_fmul_f32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_fmul
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = G_FMUL %0, %1
     $vgpr0 = COPY %2
 ...
+---
+name: test_fmul_f64
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; CHECK-LABEL: name: test_fmul
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+    ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s64) = G_FMUL %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...