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Differential D55632

AMDGPU/GlobalISel: RegBankSelect some simple operations
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Authored by arsenm on Dec 12 2018, 6:39 PM.

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tstellar
rampitec

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arsenm created this revision.Dec 12 2018, 6:39 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 12 2018, 6:39 PM
rampitec accepted this revision.Dec 12 2018, 6:49 PM

LGTM

This revision is now accepted and ready to land.Dec 12 2018, 6:49 PM
arsenm closed this revision.Dec 13 2018, 12:27 AM

r349012

Revision Contents

Diff 177986

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
setAction({G_FCMP, 1, S32}, Legal); setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal); setAction({G_FCMP, 1, S64}, Legal);
setAction({G_FMUL, S32}, Legal); setAction({G_FMUL, S32}, Legal);
setAction({G_ZEXT, S64}, Legal); setAction({G_ZEXT, S64}, Legal);
setAction({G_ZEXT, 1, S32}, Legal); setAction({G_ZEXT, 1, S32}, Legal);
setAction({G_SEXT, S64}, Legal);
setAction({G_SEXT, 1, S32}, Legal);
setAction({G_ANYEXT, S64}, Legal);
setAction({G_ANYEXT, 1, S32}, Legal);
setAction({G_FPTOSI, S32}, Legal); setAction({G_FPTOSI, S32}, Legal);
setAction({G_FPTOSI, 1, S32}, Legal); setAction({G_FPTOSI, 1, S32}, Legal);
setAction({G_SITOFP, S32}, Legal); setAction({G_SITOFP, S32}, Legal);
setAction({G_SITOFP, 1, S32}, Legal); setAction({G_SITOFP, 1, S32}, Legal);
setAction({G_FPTOUI, S32}, Legal); setAction({G_FPTOUI, S32}, Legal);
setAction({G_FPTOUI, 1, S32}, Legal); setAction({G_FPTOUI, 1, S32}, Legal);
for (LLT PtrTy : AddrSpaces) { for (LLT PtrTy : AddrSpaces) {
LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits()); LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
setAction({G_GEP, PtrTy}, Legal); setAction({G_GEP, PtrTy}, Legal);
setAction({G_GEP, 1, IdxTy}, Legal); setAction({G_GEP, 1, IdxTy}, Legal);
} }
setAction({G_ICMP, S1}, Legal); setAction({G_ICMP, S1}, Legal);
setAction({G_ICMP, 1, S32}, Legal); setAction({G_ICMP, 1, S32}, Legal);
setAction({G_CTLZ, S32}, Legal);
setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);
setAction({G_CTTZ, S32}, Legal);
setAction({G_CTTZ_ZERO_UNDEF, S32}, Legal);
setAction({G_BSWAP, S32}, Legal);
setAction({G_CTPOP, S32}, Legal);
getActionDefinitionsBuilder(G_INTTOPTR) getActionDefinitionsBuilder(G_INTTOPTR)
.legalIf([](const LegalityQuery &Query) { .legalIf([](const LegalityQuery &Query) {
return true; return true;
}); });
getActionDefinitionsBuilder(G_PTRTOINT)
.legalIf([](const LegalityQuery &Query) {
return true;
});
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalIf([=, &ST](const LegalityQuery &Query) { .legalIf([=, &ST](const LegalityQuery &Query) {
const LLT &Ty0 = Query.Types[0]; const LLT &Ty0 = Query.Types[0];
// TODO: Decompose private loads into 4-byte components. // TODO: Decompose private loads into 4-byte components.
// TODO: Illegal flat loads on SI // TODO: Illegal flat loads on SI
switch (Ty0.getSizeInBits()) { switch (Ty0.getSizeInBits()) {
case 32: case 32:
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 411 Lines • ▼ Show 20 Lines case AMDGPU::G_UNMERGE_VALUES: {
// FIXME: Shouldn't this be the default? Why do we need to handle this? // FIXME: Shouldn't this be the default? Why do we need to handle this?
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size); OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size);
} }
break; break;
} }
case AMDGPU::G_BITCAST: case AMDGPU::G_BITCAST:
case AMDGPU::G_INTTOPTR: { case AMDGPU::G_INTTOPTR:
case AMDGPU::G_PTRTOINT:
case AMDGPU::G_CTLZ:
case AMDGPU::G_CTLZ_ZERO_UNDEF:
case AMDGPU::G_CTTZ:
case AMDGPU::G_CTTZ_ZERO_UNDEF:
case AMDGPU::G_CTPOP:
case AMDGPU::G_BSWAP: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
break; break;
} }
case AMDGPU::G_TRUNC: { case AMDGPU::G_TRUNC: {
unsigned Dst = MI.getOperand(0).getReg(); unsigned Dst = MI.getOperand(0).getReg();
unsigned Src = MI.getOperand(1).getReg(); unsigned Src = MI.getOperand(1).getReg();
unsigned Bank = getRegBankID(Src, MRI, *TRI); unsigned Bank = getRegBankID(Src, MRI, *TRI);
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
break; break;
} }
case AMDGPU::G_ZEXT: { case AMDGPU::G_ZEXT:
case AMDGPU::G_SEXT:
case AMDGPU::G_ANYEXT: {
unsigned Dst = MI.getOperand(0).getReg(); unsigned Dst = MI.getOperand(0).getReg();
unsigned Src = MI.getOperand(1).getReg(); unsigned Src = MI.getOperand(1).getReg();
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
unsigned SrcBank = getRegBankID(Src, MRI, *TRI, unsigned SrcBank = getRegBankID(Src, MRI, *TRI,
SrcSize == 1 ? AMDGPU::SGPRRegBankID : SrcSize == 1 ? AMDGPU::SGPRRegBankID :
AMDGPU::VGPRRegBankID); AMDGPU::VGPRRegBankID);
unsigned DstBank = SrcBank; unsigned DstBank = SrcBank;
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: anyext_i32_to_i64_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: anyext_i32_to_i64_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[COPY]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s64) = G_ANYEXT %0
...
---
name: anyext_i32_to_i64_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: anyext_i32_to_i64_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[SEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ANYEXT %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: bswap_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: bswap_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[BSWAP:%[0-9]+]]:sgpr(s32) = G_BSWAP [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_BSWAP %0
...
---
name: bswap_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: bswap_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[BSWAP:%[0-9]+]]:vgpr(s32) = G_BSWAP [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_BSWAP %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: ctlz_zero_undef_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ctlz_zero_undef_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTLZ_ZERO_UNDEF %0
...
---
name: ctlz_zero_undef_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_zero_undef_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTLZ_ZERO_UNDEF %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: ctlz_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ctlz_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTLZ:%[0-9]+]]:sgpr(s32) = G_CTLZ [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTLZ %0
...
---
name: ctlz_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTLZ:%[0-9]+]]:vgpr(s32) = G_CTLZ [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTLZ %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: ctpop_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ctpop_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTPOP:%[0-9]+]]:sgpr(s32) = G_CTPOP [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTPOP %0
...
---
name: ctpop_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctpop_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTPOP:%[0-9]+]]:vgpr(s32) = G_CTPOP [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTPOP %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: cttz_zero_undef_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: cttz_zero_undef_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
...
---
name: cttz_zero_undef_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_zero_undef_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: cttz_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: cttz_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTTZ:%[0-9]+]]:sgpr(s32) = G_CTTZ [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTTZ %0
...
---
name: cttz_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTTZ:%[0-9]+]]:vgpr(s32) = G_CTTZ [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTTZ %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: ptrtoint_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrtoint_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[PTRTOINT:%[0-9]+]]:sgpr(p4) = G_PTRTOINT [[COPY]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(p4) = G_PTRTOINT %0
...
---
name: ptrtoint_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrtoint_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[PTRTOINT:%[0-9]+]]:vgpr(p0) = G_PTRTOINT [[COPY]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(p0) = G_PTRTOINT %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: zext_i32_to_i64_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: zext_i32_to_i64_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[COPY]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s64) = G_SEXT %0
...
---
name: zext_i32_to_i64_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: zext_i32_to_i64_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[SEXT:%[0-9]+]]:vgpr(s64) = G_SEXT [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_SEXT %0
...