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Differential D55592

[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)
ClosedPublic

Authored by rprichard on Dec 11 2018, 6:47 PM.

Details

Reviewers
srhines
eugenis
Commits
rGe028c818f5bf: [hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)
rL348983: [hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)
Summary

The change is needed to support ELF TLS in Android. See D55581 for the
same change in compiler-rt.

Diff Detail

Repository
rL LLVM

Event Timeline

rprichard created this revision.Dec 11 2018, 6:47 PM
Herald added subscribers: llvm-commits, srhines. · View Herald TranscriptDec 11 2018, 6:47 PM
Harbormaster completed remote builds in B25942: Diff 177814.Dec 11 2018, 6:47 PM
rprichard added a parent revision: D55581: Switch Android from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6).Dec 11 2018, 6:48 PM
rprichard added reviewers: srhines, eugenis.
eugenis accepted this revision.Dec 12 2018, 1:58 PM

LGTM

This revision is now accepted and ready to land.Dec 12 2018, 1:58 PM
Closed by commit rL348983: [hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6) (authored by rprichard). · Explain WhyDec 12 2018, 2:49 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Transforms/
Instrumentation/
4 lines
test/
Instrumentation/
HWAddressSanitizer/
4 lines

Diff 177937

llvm/trunk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp

Show First 20 Lines • Show All 697 Lines • ▼ Show 20 Lines UntaggedPtrLong = IRB.CreateAnd(PtrLong,
ConstantInt::get(PtrLong->getType(), ~(0xFFULL << kPointerTagShift))); ConstantInt::get(PtrLong->getType(), ~(0xFFULL << kPointerTagShift)));
} }
return UntaggedPtrLong; return UntaggedPtrLong;
} }
Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB, Type *Ty) { Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB, Type *Ty) {
Module *M = IRB.GetInsertBlock()->getParent()->getParent(); Module *M = IRB.GetInsertBlock()->getParent()->getParent();
if (TargetTriple.isAArch64() && TargetTriple.isAndroid()) { if (TargetTriple.isAArch64() && TargetTriple.isAndroid()) {
// Android provides a fixed TLS slot for sanitizers. See TLS_SLOT_SANITIZER
// in Bionic's libc/private/bionic_tls.h.
Function *ThreadPointerFunc = Function *ThreadPointerFunc =
Intrinsic::getDeclaration(M, Intrinsic::thread_pointer); Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
Value *SlotPtr = IRB.CreatePointerCast( Value *SlotPtr = IRB.CreatePointerCast(
IRB.CreateConstGEP1_32(IRB.CreateCall(ThreadPointerFunc), 0x40), IRB.CreateConstGEP1_32(IRB.CreateCall(ThreadPointerFunc), 0x30),
Ty->getPointerTo(0)); Ty->getPointerTo(0));
return SlotPtr; return SlotPtr;
} }
if (ThreadPtrGlobal) if (ThreadPtrGlobal)
return ThreadPtrGlobal; return ThreadPtrGlobal;
return nullptr; return nullptr;
▲ Show 20 Lines • Show All 247 Lines • Show Last 20 Lines

llvm/trunk/test/Instrumentation/HWAddressSanitizer/prologue.ll

Show All 23 Lines
; CHECK: entry: ; CHECK: entry:
; CHECK-IFUNC: %[[A:[^ ]*]] = call i64 asm "", "=r,0"([0 x i8]* @__hwasan_shadow) ; CHECK-IFUNC: %[[A:[^ ]*]] = call i64 asm "", "=r,0"([0 x i8]* @__hwasan_shadow)
; CHECK-IFUNC: add i64 %{{.*}}, %[[A]] ; CHECK-IFUNC: add i64 %{{.*}}, %[[A]]
; CHECK-GLOBAL: load i64, i64* @__hwasan_shadow_memory_dynamic_address ; CHECK-GLOBAL: load i64, i64* @__hwasan_shadow_memory_dynamic_address
; CHECK-TLS: %[[A:[^ ]*]] = call i8* @llvm.thread.pointer() ; CHECK-TLS: %[[A:[^ ]*]] = call i8* @llvm.thread.pointer()
; CHECK-TLS: %[[B:[^ ]*]] = getelementptr i8, i8* %[[A]], i32 64 ; CHECK-TLS: %[[B:[^ ]*]] = getelementptr i8, i8* %[[A]], i32 48
; CHECK-TLS: %[[C:[^ ]*]] = bitcast i8* %[[B]] to i64* ; CHECK-TLS: %[[C:[^ ]*]] = bitcast i8* %[[B]] to i64*
; CHECK-TLS: %[[D:[^ ]*]] = load i64, i64* %[[C]] ; CHECK-TLS: %[[D:[^ ]*]] = load i64, i64* %[[C]]
; CHECK-TLS: %[[E:[^ ]*]] = or i64 %[[D]], 4294967295 ; CHECK-TLS: %[[E:[^ ]*]] = or i64 %[[D]], 4294967295
; CHECK-TLS: = add i64 %[[E]], 1 ; CHECK-TLS: = add i64 %[[E]], 1
; "store i64" is only used to update stack history (this input IR intentionally does not use any i64) ; "store i64" is only used to update stack history (this input IR intentionally does not use any i64)
; W/o any allocas, the history is not updated, even if it is enabled explicitly with -hwasan-record-stack-history=1 ; W/o any allocas, the history is not updated, even if it is enabled explicitly with -hwasan-record-stack-history=1
; CHECK-NOT: store i64 ; CHECK-NOT: store i64
Show All 14 Lines
; CHECK: entry: ; CHECK: entry:
; CHECK-IFUNC: %[[A:[^ ]*]] = call i64 asm "", "=r,0"([0 x i8]* @__hwasan_shadow) ; CHECK-IFUNC: %[[A:[^ ]*]] = call i64 asm "", "=r,0"([0 x i8]* @__hwasan_shadow)
; CHECK-IFUNC: add i64 %{{.*}}, %[[A]] ; CHECK-IFUNC: add i64 %{{.*}}, %[[A]]
; CHECK-GLOBAL: load i64, i64* @__hwasan_shadow_memory_dynamic_address ; CHECK-GLOBAL: load i64, i64* @__hwasan_shadow_memory_dynamic_address
; CHECK-TLS: %[[A:[^ ]*]] = call i8* @llvm.thread.pointer() ; CHECK-TLS: %[[A:[^ ]*]] = call i8* @llvm.thread.pointer()
; CHECK-TLS: %[[B:[^ ]*]] = getelementptr i8, i8* %[[A]], i32 64 ; CHECK-TLS: %[[B:[^ ]*]] = getelementptr i8, i8* %[[A]], i32 48
; CHECK-TLS: %[[C:[^ ]*]] = bitcast i8* %[[B]] to i64* ; CHECK-TLS: %[[C:[^ ]*]] = bitcast i8* %[[B]] to i64*
; CHECK-TLS: %[[D:[^ ]*]] = load i64, i64* %[[C]] ; CHECK-TLS: %[[D:[^ ]*]] = load i64, i64* %[[C]]
; CHECK-NOHISTORY-NOT: store i64 ; CHECK-NOHISTORY-NOT: store i64
; CHECK-HISTORY: %[[PTR:[^ ]*]] = inttoptr i64 %[[D]] to i64* ; CHECK-HISTORY: %[[PTR:[^ ]*]] = inttoptr i64 %[[D]] to i64*
; CHECK-HISTORY: store i64 %{{.*}}, i64* %[[PTR]] ; CHECK-HISTORY: store i64 %{{.*}}, i64* %[[PTR]]
; CHECK-HISTORY: %[[D1:[^ ]*]] = ashr i64 %[[D]], 56 ; CHECK-HISTORY: %[[D1:[^ ]*]] = ashr i64 %[[D]], 56
Show All 17 Lines