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[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
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Authored by olista01 on Sep 30 2014, 1:54 AM.

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rengolin
Summary

The Cortex-M7 has 3 options for it's FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features.

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olista01 updated this revision to Diff 14205.Sep 30 2014, 1:54 AM
olista01 retitled this revision from to [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM).
olista01 updated this object.
olista01 edited the test plan for this revision. (Show Details)
olista01 set the repository for this revision to rL LLVM.
olista01 added a subscriber: Unknown Object (MLST).
rengolin added inline comments.
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
8806

It's not a full NEON, is it? The M7 page only talks about 8/16-bit DSP related SIMD.

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
851

typo: identical

olista01 added inline comments.Sep 30 2014, 5:41 AM
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
8806

The third member of this struct is the set of features to disable, so this is enabling {FPARMv8, D16} and disabling {NEON, Crypto}.

olista01 updated this revision to Diff 14217.Sep 30 2014, 5:42 AM

Fixed typo

rengolin accepted this revision.Sep 30 2014, 10:43 AM
rengolin added a reviewer: rengolin.

Ha, yes. LGTM.Thanks!

This revision is now accepted and ready to land.Sep 30 2014, 10:43 AM
olista01 closed this revision.Oct 1 2014, 2:12 AM

Committed revision 218747.